Evaluation of Stacked Nanowires Transistors for CMOS: Performance and Technology Opportunities

机译：CMOS堆叠纳米线晶体管的评估：性能和技术机会

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Stacked-NW FETs pave the way for significant increase in device effective width over FinFET and FDSOI. An increase of performance and/or a decrease of device footprint is expected by using thin and wide NW channels also known as nanosheets or nanoplates. This paper points out Gate Last integration issues of stacked-NWs. Two solutions labeled as NW First and NW Last are presented featuring internal spacer formation. A demonstration of self-aligned gate and spacers is proposed, involving Hydrogen Silsesquioxane (HSQ) lithography through silicon channels.

机译：堆叠式NW FET大大提高了FinFET和FDSOI器件的有效宽度。通过使用又薄又宽的NW通道（也称为纳米片或纳米板），可以预期性能提高和/或设备占用空间减少。本文指出了堆叠式NW的Gate Last集成问题。提出了两种标记为NW First和NW Last的解决方案，它们具有内部间隔物的形成。提出了一种自对准栅极和隔离层的演示，其中涉及通过硅通道的氢倍半硅氧烷（HSQ）光刻。

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《Silicon compatible materials, processes, and technologies for advanced integrated circuits and emerging applications 6》|2016年|43-54|共12页
会议地点 San Diego(US)
作者
L. Gaben; S. Barraud; M.-P. Samson; M.-A. Jaud; S. Martinie; O. Rozeau; J. Lacord; C. Arvet; C. Vizioz; J. Bustoss; J.-A. Dallery; S. Pauliac; V. Balan; C. Euvrard; C. Perrot; V. Loup; P. Besson; J.-M. Hartmann; S. Monfray; F. Boeuf; T. Skotnicki; F. Balestra; M. Vinet;
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STMicroelectronics, 850 rue J. Monnet, 38920 Crolles, France,CEA-LETI, Minatec campus, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France,IMEP-LAHC, 3 parvis Louis Neel, BP257, 38016 Grenoble Cedex 1, France;

CEA-LETI, Minatec campus, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France;

STMicroelectronics, 850 rue J. Monnet, 38920 Crolles, France;

CEA-LETI, Minatec campus, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France;

CEA-LETI, Minatec campus, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France;

CEA-LETI, Minatec campus, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France;

CEA-LETI, Minatec campus, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France;

STMicroelectronics, 850 rue J. Monnet, 38920 Crolles, France;

CEA-LETI, Minatec campus, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France;

STMicroelectronics, 850 rue J. Monnet, 38920 Crolles, France;

CEA-LETI, Minatec campus, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France;

CEA-LETI, Minatec campus, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France;

CEA-LETI, Minatec campus, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France;

CEA-LETI, Minatec campus, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France;

CEA-LETI, Minatec campus, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France;

CEA-LETI, Minatec campus, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France;

CEA-LETI, Minatec campus, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France;

CEA-LETI, Minatec campus, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France;

STMicroelectronics, 850 rue J. Monnet, 38920 Crolles, France;

STMicroelectronics, 850 rue J. Monnet, 38920 Crolles, France;

STMicroelectronics, 850 rue J. Monnet, 38920 Crolles, France;

IMEP-LAHC, 3 parvis Louis Neel, BP257, 38016 Grenoble Cedex 1, France;

CEA-LETI, Minatec campus, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France;

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3. Vertically Stacked SiGe Nanowire Array Channel CMOS Transistors [J] . W. W. Fang, N. Singh, L. K. Bera, IEEE Electron Device Letters . 2007,第期

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4. Evaluation of Stacked Nanowires Transistors for CMOS: Performance and Technology Opportunities [C] . L. Gaben, S. Barraud, M.-P. Samson, Meeting of The Electrochemical Society . 2016

机译：CMOS堆叠纳米线晶体管评估：性能和技术机会
5. High-Performance, Low-Power, and Compact CMOS VLSI Circuits with Carbon Nanotube Transistor Technology [D] . Sun, Yanan. 2014

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6. CMOS-Compatible Silicon Nanowire Field-Effect Transistor Biosensor: Technology Development toward Commercialization [O] . Duy Phu Tran, Thuy Thi Thanh Pham, Bernhard Wolfrum, 2018

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7. Simulation study of vertically stacked lateral Si nanowires transistors for 5 nm CMOS applications [O] . Al-Ameri Talib, Georgiev V.P., Adamu-Lema F., 2017

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Evaluation of Stacked Nanowires Transistors for CMOS: Performance and Technology Opportunities

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