Simulation based development of EEPROM devices within a 0.35μm process

机译：0.35μm工艺内基于EEPROM器件的仿真开发

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This paper outlines the capabilities of 2D process and device simulation in the development of byte-eraseable EEPROMs within a 0.35μm CMOS process. Evaluation of different cell options, investigation of critical design rules and process development have been successfully undertaken. Simulation has been shown to provide useful insight and understanding that cannot be obtained from measurements alone and can increase the speed of the design cycle.

机译：本文概述了在0.35μmCMOS工艺中开发字节可擦除EEPROM时2D工艺和器件仿真的功能。已成功进行了各种单元选项的评估，关键设计规则的调查和工艺开发。事实证明，仿真可以提供有用的见解和理解，而这不能仅从测量中获得，并且可以提高设计周期的速度。

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来源
《Simulation of semiconductor processes and devices 1998(SISPAD98)》|1998年|376-379|共4页
会议地点 Leuven(BE);Leuven(BE)
作者
R. Duffy; A. Concannon; A. Mathewson; C. de Graaf; M. Slotboom; R. Verhaar;
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作者单位

National Microelectronics Research Centre, Lee Maltings, Prospect Row, Cork, Ireland;

National Microelectronics Research Centre, Lee Maltings, Prospect Row, Cork, Ireland;

National Microelectronics Research Centre, Lee Maltings, Prospect Row, Cork, Ireland;

Philips Research Laboratories, Prof. Holstlaan 4, 5656 AA Eindhoven, The Netherlands;

Philips Research Laboratories, Prof. Holstlaan 4, 5656 AA Eindhoven, The Netherlands;

Philips Research Laboratories, Prof. Holstlaan 4, 5656 AA Eindhoven, The Netherlands;

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原文格式 PDF
正文语种 eng
中图分类半导体器件制造工艺及设备;
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Simulation based development of EEPROM devices within a 0.35μm process

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