Rigorous Capacitance Simulation of DRAM Cells

机译：DRAM单元的严格电容仿真

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As dynamic RAM cell size is being scaled down, the storage capacitor design becomes more difficult because its capacitance cannot scale as much. The solutions are leading to complex structures which require an accurate description of the fabrication process, making technology CAD (TCAD) simulations necessary. We introduce a set of layout-driven TCAD tools to perform capacitance extraction of three-dimensional structures created by rigorous topographic simulation, suitable in the development of new cell configurations. Simulation results are also given and compared with measured data.

机译：随着动态RAM单元尺寸的缩小，存储电容器的设计变得更加困难，因为其电容无法达到同样的规模。解决方案导致了复杂的结构，需要对制造过程进行准确的描述，从而使技术CAD（TCAD）模拟成为必要。我们引入了一组布局驱动的TCAD工具，以执行通过严格的地形仿真创建的三维结构的电容提取，适用于开发新的单元配置。还给出了仿真结果，并将其与测量数据进行了比较。

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来源
《Simulation of semiconductor processes and devices 1998(SISPAD98)》|1998年|69-72|共4页
会议地点 Leuven(BE);Leuven(BE)
作者
R. Martins; R. Sabelka; W. Pyka; S. Selberherr;
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作者单位

Institute for Microelectronics, TU Vienna Gusshausstr. 27-29, A-1040 Vienna, Austria;

Institute for Microelectronics, TU Vienna Gusshausstr. 27-29, A-1040 Vienna, Austria;

Institute for Microelectronics, TU Vienna Gusshausstr. 27-29, A-1040 Vienna, Austria;

Institute for Microelectronics, TU Vienna Gusshausstr. 27-29, A-1040 Vienna, Austria;

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正文语种 eng
中图分类半导体器件制造工艺及设备;
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机译：DRam单元的严格电容模拟

Rigorous Capacitance Simulation of DRAM Cells

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