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首页> 外文会议>Simulation of semiconductor processes and devices 1998(SISPAD98) >Accurate Layout-Based Interconnect Analysis
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Accurate Layout-Based Interconnect Analysis

机译：基于布局的准确互连分析

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摘要

We have developed a set of simulation programs for two- and three-dimensional analysis of interconnect structures. The simulators are based on the finite element method and can be used for highly accurate capacitance extraction, resistance calculation, transient electric simulation (calculation of capacitive crosstalk and delay times), and coupled electro-thermal simulations. The layout of the interconnect structure can be imported from CIF or GDSII files, or can be created interactively with a graphical layout editor which is also used to select an "area of interest" and to generate cuts for two-dimensional simulations. The geometric structure can be generated either directly from the layout by specifying constant layer thicknesses, or by a rigorous topography simulation. For the creation of two-dimensional simulation grids the program Triangle is used, for the three-dimensional case we perform a layer-based grid generation method. As application example a polysilicon resistor pair is analyzed with the tools presented.
机译：我们已经开发了一套用于互连结构的二维和三维分析的仿真程序。这些仿真器基于有限元方法，可用于高精度电容提取，电阻计算，瞬态电仿真（电容串扰和延迟时间的计算）以及耦合电热仿真。互连结构的布局可以从CIF或GDSII文件中导入，也可以使用图形布局编辑器进行交互创建，该图形编辑器还可以用于选择“关注区域”并生成二维仿真的切口。可以通过指定恒定的层厚度直接从布局中生成几何结构，也可以通过严格的地形模拟生成几何结构。为了创建二维仿真网格，使用了Triangle程序，对于三维情况，我们执行了基于图层的网格生成方法。作为应用示例，使用提供的工具对多晶硅电阻对进行了分析。

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