The vertical heterojunction MOSFET

机译：垂直异质结MOSFET

获取原文

获取原文并翻译 | 示例

页面导航

摘要
著录项
相似文献
相关主题

摘要

In this paper a new vertical MOS transistor structure including its fabrication and electrical results will be presented. It overcomes the technological and physical limitations encountered when scaling the classical planar transistor into the deep submicron regime. It solves the technological issue by defining the channel length through epitaxial growth instead of lithography. The physical phenomenon of drain induced barrier lowering (DIBL) is largely decreased through the use of a heterojunction between source and drain.

机译：本文将介绍一种新的垂直MOS晶体管结构，包括其制造和电学结果。它克服了将传统的平面晶体管缩放到深亚微米范围时遇到的技术和物理限制。它通过外延生长而不是光刻来定义沟道长度来解决技术问题。通过使用源极和漏极之间的异质结，可以大大降低漏极引起的势垒降低（DIBL）的物理现象。

著录项

来源
《Thin films epitaxial growth and nanostructures》|1998年|p.299-305|共7页
会议地点 Strasbourg(FR)
作者
Kristin De Meyer; Matty Caymax; Nadine Collaert; Roger Loo; Peter Verheyen;
展开▼
作者单位

展开▼
会议组织
原文格式 PDF
正文语种 eng
中图分类一般工业技术;
关键词
Drain induced barrier lowering (DIBL); Metal oxide semiconductor;

机译：排水诱导的势垒降低（DIBL）；金属氧化物半导体;

相似文献

外文文献
中文文献
专利

1. Novel vertical power MOSFET with partial GaN/Si heterojunction to improve breakdown voltage by breakdown point transfer terminal technology [J] . Wang Xiameng, Duan Baoxing, Yang Xin, Semiconductor science and technology . 2020,第10期

机译：具有部分GaN / Si异质结的新型垂直功率MOSFET通过击穿点传输终端技术提高击穿电压
2. Vertical heterojunction Ge_(0.92)Sn_(0.08)/Ge gate-all-around nanowire pMOSFETs with NiGeSn contact [J] . Liu Mingshan, Mertens Konstantin, von den Driesch Nils, Solid-State Electronics . 2020,第Juna期

机译：垂直异相结合GE_（0.08）SN_（0.08）/ GE门 - 全面与nigesn接触的纳米线PMOSFET
3. Modeling the short-channel threshold voltage of a novel vertical heterojunction pMOSFET [J] . Collaert N., De Meyer K. IEEE Transactions on Electron Devices . 1999,第5期

机译：模拟新型垂直异质结pMOSFET的短通道阈值电压
4. Vertical heterojunction InAs/InGaAs nanowire MOSFETs on Si with Ion = 330 μA/μm at Ioff = 100 nA/μm and VD = 0.5 V [C] . Olli-Pekka Kilpi, Jun Wu, Johannes Svensson, IEEE Symposium on VLSI Technology . 2017

机译：Si上的垂直异质结InAs / InGaAs纳米线MOSFET，Ioff = 100 nA /μm且VD = 0.5 V时Ion = 330μA/μm
5. Vertical surrounding-gate MOSFETs incorporating silicon germanium heterojunctions. [D] . Date, Celisa Kelly. 2001

机译：结合了硅锗异质结的垂直环绕栅MOSFET。
6. Fabrication and Characteristics of an nc-Si/c-Si Heterojunction MOSFETs Pressure Sensor [O] . Xiaofeng Zhao, Dianzhong Wen, Gang Li 2012

机译：nc-Si / c-Si异质结MOSFET压力传感器的制造和特性
7. Understanding the Leakage Mechanisms and Breakdown Limits of Vertical GaN-on-Si p+n−n Diodes: The Road to Reliable Vertical MOSFETs [O] . Kalparupa Mukherjee, Carlo De Santi, Matteo Buffolo, 2021

机译：了解垂直GAN-on-Si P + N-N二极管的泄漏机制和分解限制：可靠垂直MOSFET的道路

The vertical heterojunction MOSFET

摘要

著录项

相似文献

相关主题

期刊订阅