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首页> 外文会议>VLSI, 2009. ISVLSI '09 >A New Placement Algorithm for Reduction of Soft Errors in Macrocell Based Design of Nanometer Circuits
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A New Placement Algorithm for Reduction of Soft Errors in Macrocell Based Design of Nanometer Circuits

机译：基于纳米电路设计的减少宏单元软错误的新布局算法

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The rates of transient faults such as soft errors have been significantly impacted due to the aggressive scaling trends in the nanometer regime. In the past, several circuit optimization techniques have been proposed for preventing soft errors in logic circuits. These approaches include, inclusion of concurrent error detection circuits on selective nodes, selective gate sizing, dual-VDD assignment and selective node hardening at the transistor level. However, we show in this paper that larger wirelengths for nets can act as larger RC ladders and can effectively filter out the transient glitches due to radiation strikes. Based on this, we propose a simulated annealing based placement algorithm that significantly reduces the SER of logic circuits. We accurately capture the soft error masking effects by using a new metric called the logical observability. The cost function for simulated annealing is modeled as the summation of the logical observability weighted with the netlength for each net, while simultaneously constraining the total area and the total wirelength. The algorithm tries to assign higher wirelengths for nets with low masking probability for higher glitch reduction, while maintaining low delay and area penalty for the overall circuit. Each placement configuration is represented as a sequence pair and the moves in the space of sequence pairs are probabilistically accepted depending upon the cost gradient and the iteration count. Higher cost moves have a higher probability of acceptance at initial iterations for better state space exploration, while at later iterations the algorithm greedily tries to minimize the cost. To the best of our knowledge, this is the first time that soft error rate reduction is attempted during the placement stage. The proposed algorithm has been implemented and validated on the ISCAS85 benchmarks. We have experimented using the FreePDK 45nm Process Design Kit and the OSU cell library which indicate that our radiation immune plac-nement algorithm can significantly reduce the SER in logic circuits with very low overheads in delay and area.
机译：诸如软错误之类的瞬态故障的发生率由于纳米范围内的侵蚀性缩放趋势而受到显着影响。过去，已经提出了几种电路优化技术来防止逻辑电路中的软错误。这些方法包括在选择性节点上包含并发错误检测电路，选择性栅极大小调整，双VDD分配以及晶体管级的选择性节点硬化。但是，我们在本文中表明，网的较大线长可以充当较大的RC梯形图，并且可以有效滤除由于辐射冲击而引起的瞬态毛刺。基于此，我们提出了一种基于模拟退火的布局算法，该算法显着降低了逻辑电路的SER。我们使用称为逻辑可观察性的新指标来准确捕获软错误掩盖效果。模拟退火的成本函数被建模为逻辑可观察性的总和，每个逻辑网的净长加权，同时限制总面积和总线长。该算法尝试为具有较低掩蔽概率的网络分配较高的线长，以降低毛刺，同时为整个电路保持较低的延迟和面积损失。每个放置配置都表示为一个序列对，并根据成本梯度和迭代次数概率性地接受序列对空间中的移动。成本较高的移动在初始迭代中具有较高的接受概率，以进行更好的状态空间探索，而在后续迭代中，该算法会贪婪地尝试将成本最小化。据我们所知，这是首次在放置阶段尝试降低软错误率。所提出的算法已在ISCAS85基准上得到实施和验证。我们已经使用FreePDK 45nm工艺设计套件和OSU单元库进行了实验，这些结果表明，我们的辐射免疫定位算法可以显着减少逻辑电路中的SER，而延迟和面积方面的开销却非常低。

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