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A LOW-POWER, 32-BIT RISC PROCESSOR WITH SIGNAL PROCESSING CAPABILITY AND ITS MULTIPLY-ADDER

机译：具有信号处理能力的低功耗32位RISC处理器及其乘法器

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A 500 mW, 100 MHz, 32-bit RISC microprocessor, designed for software signal processing is described. Its signal processing oriented instruction set includes fast integer/fixed-point multiply/multiply-accumulate instructions, minimum/maximum instructions and conditional branch instructions with prediction etc. The processor integrates a 200 MHz, 32-bit compact multiply-adder with a parallel overflow detector in its pipeline to achieve peak signal processing performance of 200 MOPS. Through the employment of this fast multiply-adder, this microprocessor is able to obtain higher signal processing performance than other RISC processors.

机译：描述了设计用于软件信号处理的500 mW，100 MHz，32位RISC微处理器。其面向信号处理的指令集包括快速整数/定点乘法/乘法累加指令，最小/最大指令和带预测的条件分支指令。处理器集成了200 MHz，32位紧凑乘法加法器和并行溢出检测器在其管线中实现200 MOPS的峰值信号处理性能。通过使用这种快速乘法加法器，该微处理器能够获得比其他RISC处理器更高的信号处理性能。

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来源
《VLSI signal processing, VIII》|1995年|51-60|共10页
会议地点 Sakai(JP)
作者
Kouhei Nadehara; Mivvako Hayashida; Ichiro Kuroda;
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作者单位

Information Technology Research Labs., NEC Corporation 4-1-1, Miyazaki, Miyamae-ku, Kawasaki 216, Japan;

Kyushu LSI Developmemt Center, NEC IC Microcomputer Systems, Ltd. 2081-24, Tabaru, Mashiki-machi, Kamimashiki-gun, Kumamoto 861-22, Japan;

Information Technology Research Labs., NEC Corporation 4-1-1, Miyazaki, Miyamae-ku, Kawasaki 216, Japan;

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原文格式 PDF
正文语种 eng
中图分类微电子学、集成电路（IC）;通信理论;
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4. A low-power, 32-bit RISC processor with signal processing capability and its multiply-adder [C] . Nadehara, K., Hayashida, . 1995

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A LOW-POWER, 32-BIT RISC PROCESSOR WITH SIGNAL PROCESSING CAPABILITY AND ITS MULTIPLY-ADDER

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