Verilog Implementation of a MIPS RISC 32-bit Pipelined Processor Architecture

P. Indira; Ved Vyas Dwivedi; M. Kamaraju

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Verilog Implementation of a MIPS RISC 32-bit Pipelined Processor Architecture

机译：Verilog实现MIPS RISC 32位流水线处理器架构

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Pipelining is a design implementation concept, where elements of a pipeline are often executed in parallel (or) in time-segmented fashion with pipeline registers used as buffer storage. In this work, 3 stage pipelined architecture with 32-bit MIPS RISC processor is used to optimize the design throughput. The high performance features compromise the trade-off between power and speed requirement. In this paper, the possible hazards, and issues with remedies are discussed. In comparative study, different device parameters are compared especially, Power is very much minimized and speed is enhanced when compared to its counterparts. The simulation is carried out with Xilinx 14.3 ISE suite with Verilog HDL coding. MATLAB tool is employed to represent the relationship of various parameters involved in it.

机译：流水线是一种设计实现概念，其中管道的元素通常以时间分段方式并行（或）执行，其中管道寄存器用作缓冲存储器。在这项工作中，3阶段流水线架构，带32位MIPS RISC处理器用于优化设计吞吐量。高性能特点会损害电力和速度要求之间的权衡。在本文中，讨论了可能的危险和补救措施的问题。在比较研究中，特别地比较了不同的装置参数，并且与其对应物相比，功率非常最小，并且速度增强。使用Verilog HDL编码进行Xilinx 14.3 ISE套件进行模拟。 MATLAB工具用于代表其涉及的各种参数的关系。

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来源
《IOSR Journal of Electronics and Communication Engineering》 |2019年第1期|31-40|共10页
作者
P. Indira; Ved Vyas Dwivedi; M. Kamaraju;
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作者单位

ECE Department CU Shah University India;

ECE Department CU Shah University India;

ECE Department Gudlavalleru Engg. College JNT University India;

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原文格式 PDF
正文语种 eng
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关键词
MIPS RISC Processor; Verilog HDL coding; MATLAB tool; Xilinx;

机译：MIPS RISC处理器;Verilog HDL编码;matlab工具;Xilinx.;

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专利

1. Verilog Implementation of a MIPS RISC 32-bit Pipelined Processor Architecture [J] . P. Indira, Ved Vyas Dwivedi, M. Kamaraju IOSR Journal of Electronics and Communication Engineering . 2019,第1期

机译：MIPS RISC 32位流水线处理器体系结构的Verilog实现
2. Design and Implementation of Synthesizable 32-bit Four Stage Pipelined RISC Processor in FPGA Using Verilog/VHDL [J] . Bikash Poduel, Prasanna Kansakar, Sujit R. Chhetri, Nepal Journal of Science and Technology . 2015,第1期

机译：基于Verilog / VHDL的FPGA中可综合的32位四级流水线RISC处理器的设计与实现
3. Design and Analysis of A 32-bit Pipelined MIPS Risc Processor [J] . P. Indira, M. Kamaraju, Ved Vyas Dwivedi International Journal of VLSI Design & Communication Systems . 2019,第5期

机译：32位流水线MIPS Risc处理器的设计与分析
4. Design and Implementation of 32-bit MIPS-Based RISC Processor [C] . Sumit Patra, Sunil Kumar, Swati Verma, International conference on VLSI, communication, and signal processing . 2020

机译：基于32位MIPS的RISC处理器的设计与实现
5. Pipeline FFT architecture implementation using Verilog HDL. [D] . Murukutla, Bhavishya. 2013

机译：使用Verilog HDL的管道FFT架构实现。
6. A wavelet-based ECG delineation algorithm for 32-bit integer online processing [O] . Luigi Y Di Marco, Lorenzo Chiari 2011

机译：基于小波的ECG描绘算法用于32位整数在线处理
7. Design and Analysis of A 32-bit Pipelined MIPS Risc Processor [O] . Ved Vyas Dwivedi 2019

机译：32位管道MIPS RISC处理器的设计与分析

Verilog Implementation of a MIPS RISC 32-bit Pipelined Processor Architecture

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