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首页> 外文会议>VLSI Test Symposium, 2009. VTS '09 >RT-Level Deviation-Based Grading of Functional Test Sequences
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RT-Level Deviation-Based Grading of Functional Test Sequences

机译：基于RT级偏差的功能测试序列分级

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摘要

Functional test sequences are often used in manufacturing testing to target defects that are not detected by structural test. Therefore, it is necessary to evaluate the quality of functional test sequences. However, it is very time-consuming to evaluate the quality of functional test sequences by gate-level fault simulation. Therefore, we propose output deviations as a metric to grade functional test sequences at the register transfer (RT)-level without explicit fault simulation. Experimental results for the open-source Parwan processor and the Scheduler module of the Illinois Verilog Model (IVM) show that the deviations metric is computationally efficient and it correlates well with gate-level coverage for stuck-at, transition-delay, and bridging faults. Results also show that functional test sequences that are reordered based on output deviations provide steeper gate-level fault coverage ramp-up compared to other ordering methods.
机译：功能测试序列通常用于制造测试中，以针对结构测试未检测到的缺陷。因此，有必要评估功能测试序列的质量。但是，通过门级故障仿真评估功能测试序列的质量非常耗时。因此，我们提出了输出偏差作为度量，以在寄存器传输（RT）级别上对功能测试序列进行分级，而无需进行明确的故障仿真。对伊利诺伊州Verilog模型（IVM）的开源Parwan处理器和Scheduler模块的实验结果表明，偏差度量在计算上是有效的，并且与卡住，过渡延迟和桥接故障的门级覆盖率很好地相关。结果还表明，与其他排序方法相比，基于输出偏差重新排序的功能测试序列可提供更陡峭的门级故障覆盖率提升。

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