A Scalable, Digital BIST Circuit for Measurement and Compensation of Static Phase Offset

著录项

• 来源
  《VLSI Test Symposium, 2009. VTS '09》|2009年|185-188|共4页
• 会议地点 Santa Cruz CA(US);Santa Cruz CA(US)
• 作者

  Jenkins K.A.; Li L.;

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• 作者单位

  IBM T.J. Watson Res. Center, Yorktown Heights, NY, USA;

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• 会议组织
• 原文格式 PDF
• 正文语种
• 中图分类
• 关键词

  CMOS digital integrated circuits; built-in self test; calibration; digital phase locked loops; nanoelectronics; CMOS technology; digital BIST circuit; digital element; digital scan chain; feedback signal; frequency 1 GHz; on-chip calibration; on-chip circuit design; phase-locked loop; power 3 mW; reference clock frequency; scalable circuit; size 65 nm; static phase offset compensation; static phase offset measurement; voltage 1.0 V; PLL; built-in self-test; on-chip measurement; static phase error; static phase offset;

  机译：CMOS数字集成电路;内置自检;校准;数字锁相环;纳米电子; CMOS技术;数字BIST电路;数字元件;数字扫描链;反馈信号;频率1 GHz;片内校准;片上电路设计;锁相环;功率3 mW;参考时钟频率;可扩展电路;尺寸65 nm;静态相位偏移补偿;静态相位偏移测量;电压1.0 V; PLL;内置自测试;片内测量;静态相位误差;静态相位偏移;