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Compact Delay Test Generation with a Realistic Low Cost Fault Coverage Metric

机译：紧凑的延迟测试生成，具有现实的低成本故障覆盖率指标

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摘要

This paper proposes a realistic low cost fault coverage metric targeting both global and local delay faults. It suggests the test strategy of generating a different number of the longest paths for each line in the circuit while maintaining high fault coverage. This metric has been integrated into the CodGen ATPG tool. Experimental results show significant reductions in test generation time and vector count on ISCAS89 and industry designs.

机译：本文提出了一种针对全局和局部延迟故障的低成本低成本故障覆盖指标。它提出了一种测试策略，即在保持高故障覆盖率的同时，为电路中的每条线路生成不同数量的最长路径。该指标已集成到CodGen ATPG工具中。实验结果表明，在ISCAS89和行业设计中，测试生成时间和向量数量显着减少。

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来源
《VLSI Test Symposium, 2009. VTS '09》|2009年|59-64|共6页
会议地点 Santa Cruz CA(US);Santa Cruz CA(US)
作者
Zheng Wang; Walker D.M.H.;
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作者单位

Dept. of Comput. Sci. Eng., Texas AM Univ., College Station, TX, USA;

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关键词
automatic test pattern generation; circuit testing; delay circuits; fault diagnosis; CodGen ATPG tool; ISCAS89; compact delay test generation; global delay faults; high fault coverage; industry design; local delay faults; realistic low cost fault coverage metric; test generation time reduction; ATPG; delay test; fault coverage metric;

机译：自动测试模式生成;电路测试;延迟电路;故障诊断; CodGen ATPG工具; ISCAS89;紧凑型延迟测试生成;全局延迟故障;高故障覆盖率;行业设计;局部延迟故障;现实的低成本故障覆盖率;测试生成时间减少; ATPG;延迟测试;故障覆盖率;

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专利

1. Diagnosis of path delay faults based on low-coverage tests [J] . Pomeranz I., Reddy S.M. Computers & Digital Techniques, IET . 2010,第2期

机译：基于低覆盖率测试的路径延迟故障诊断
2. Function-based compact test pattern generation for path delay faults [J] . Michael M.K., Tragoudas S. IEEE transactions on very large scale integration (VLSI) systems . 2005,第8期

机译：基于功能的紧凑测试模式生成，用于路径延迟故障
3. On the Use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test Generation [J] . Kyriakos Christou, Maria K. Michael, Spyros Tragoudas Journal of Electronic Testing: Theory and Applications: Theory and Applications . 2008,第1a3期

机译：使用ZBDD进行隐式和紧凑型关键路径延迟故障测试生成
4. Compact Delay Test Generation with a Realistic Low Cost Fault Coverage Metric [C] . Zheng Wang, D. M. H. Walker IEEE VLSI Test Symposium . 2009

机译：紧凑型延迟试验，具有实际低成本故障覆盖度量
5. Compaction mechanism to reduce test pattern counts and segmented delay fault testing for path delay faults [D] . Jha, Sharada 2013

机译：压缩机制可减少测试模式计数，并针对路径延迟故障进行分段延迟故障测试
6. A testing-coverage software reliability model considering fault removal efficiency and error generation [O] . Qiuying Li, Hoang Pham 2011

机译：考虑故障排除效率和错误产生的测试覆盖软件可靠性模型
7. A Statistical Fault Coverage Metric for Realistic Path Delay Faults [O] . Wangqi Qiu, Xiang Lu, Jing Wang, 2004

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Compact Delay Test Generation with a Realistic Low Cost Fault Coverage Metric

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