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Performance Evaluation of FMOSSIM, a Concurrent Switch-Level Fault Simulator

机译：并行开关级故障模拟器FMOSSIM的性能评估

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This paper presents measurements obtained while performing fault simulations of MOS circuits modeled at the switch level. In this model the transistor structure of the circuit is represented explicitly as a network of charge storage nodes connected by bidirectional transistor switches. Since the logic model of the simulator closely matches the actual structure of MOS circuits, such faults as stuck-open and closed transistors as well as short and open-circuited wires can be simulated. By using concurrent simulation techniques, we obtain a performance level comparable to fault simulators using logic gate models. Our measurements indicate that fault simulation times grow as the product of the circuit size and number of patterns, assuming the number of faults to be simulated is proportional to the circuit size. However, fault simulation times depend strongly on the rate at which the test patterns detect the faults.
机译：本文介绍了在对开关级建模的MOS电路进行故障仿真时获得的测量结果。在该模型中，电路的晶体管结构明确表示为通过双向晶体管开关连接的电荷存储节点网络。由于仿真器的逻辑模型与MOS电路的实际结构紧密匹配，因此可以模拟诸如晶体管的开路和关断以及导线的短路和开路等故障。通过使用并行仿真技术，我们可以获得与使用逻辑门模型的故障仿真器相当的性能水平。我们的测量结果表明，假设要模拟的故障数量与电路尺寸成正比，故障仿真时间随电路尺寸和图形数量的乘积而增长。但是，故障模拟时间很大程度上取决于测试模式检测故障的速率。

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