Scope and Method of Study. The intent of the thesis is to determine if there is a tradeoff between implementing memory design techniques of multiple port versus multiple bank memory. I have designed twenty-one layouts to show the relationship and trade-offs that different memory techniques can provide for SRAM. The designs are created in Cadence Virtuoso Layout Editor. Results are extracted and tested with Cadence HSPICE, Synopsis Nanosim, and IRSIM. The technology library that is used in the thesis designs is AMI 0.60u C5N.;Findings and Conclusions. The delay performance and area of the multi-bank and multi-port memory are compared to each other in order to reveal trade offs between the two techniques. Multi-bank and multi-port reach an optimal equivalent trade off point at any port size with a memory area of 65536 which is about 256x256 in multi-port and 32x64x8banks in multi-bank.
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