• 主题
高级搜索  >
历史搜索 清空历史
首页> 美国卫生研究院文献>Nanotechnology Science and Applications >Power optimized variation aware dual-threshold SRAM cell design technique
【2h】

Power optimized variation aware dual-threshold SRAM cell design technique

机译：功耗优化的变化感知双阈值SRAM单元设计技术

代理获取
本网站仅为用户提供外文OA文献查询和代理获取服务，本网站没有原文。下单后我们将采用程序或人工为您竭诚获取高质量的原文，但由于OA文献来源多样且变更频繁，仍可能出现获取不到、文献不完整或与标题不符等情况，如果获取不到我们将提供退款服务。请知悉。
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

Bulk complementary metal-oxide semiconductor (CMOS) technology is facing enormous challenges at channel lengths below 45 nm, such as gate tunneling, device mismatch, random dopant fluctuations, and mobility degradation. Although multiple gate transistors and strained silicon devices overcome some of the bulk CMOS problems, it is sensible to look for revolutionary new materials and devices to replace silicon. It is obvious that future technology materials should exhibit higher mobility, better channel electrostatics, scalability, and robustness against process variations. Carbon nanotube-based technology is very promising because it has most of these desired features. There is a need to explore the potential of this emerging technology by designing circuits based on this technology and comparing their performance with that of existing bulk CMOS technology. In this paper, we propose a low-power variation-immune dual-threshold voltage carbon nanotube field effect transistor (CNFET)-based seven-transistor (7T) static random access memory (SRAM) cell. The proposed CNFET-based 7T SRAM cell offers ∼1.2× improvement in standby power, ∼1.3× improvement in read delay, and ∼1.1× improvement in write delay. It offers narrower spread in write access time (1.4× at optimum energy point [OEP] and 1.2× at 1 V). It features 56.3% improvement in static noise margin and 40% improvement in read static noise margin. All the simulation measurements are taken at proposed OEP decided by the optimum results obtained after extensive simulation on HSPICE (high-performance simulation program with integrated circuit emphasis) environment.
机译：体互补金属氧化物半导体（CMOS）技术在低于45 nm的沟道长度方面面临着巨大挑战，例如栅极隧穿，器件失配，随机掺杂物波动和迁移率降低。尽管多个栅极晶体管和应变硅器件克服了一些大型CMOS问题，但明智的做法是寻找革命性的新材料和器件来替代硅。显然，未来的技术材料应表现出更高的迁移率，更好的沟道静电性能，可扩展性以及对工艺变化的抵抗力。基于碳纳米管的技术非常有前途，因为它具有这些所需的大多数功能。有必要通过设计基于该技术的电路并将其性能与现有的块状CMOS技术相比较来探索这种新兴技术的潜力。在本文中，我们提出了一种基于低功率变化免疫的双阈值碳纳米管场效应晶体管（CNFET）的七晶体管（7T）静态随机存取存储器（SRAM）单元。所提出的基于CNFET的7T SRAM单元可将待机功耗提高约1.2倍，将读取延迟提高约1.3倍，将写入延迟提高约1.1倍。它提供了更窄的写访问时间扩展（最佳能量点[OEP]为1.4倍，1 V为1.2倍）。它的静态噪声容限提高了56.3％，读取静态噪声容限提高了40％。所有的仿真测量都是在建议的OEP上进行的，该OEP取决于在HSPICE（具有集成电路重点的高性能仿真程序）环境下进行广泛仿真后获得的最佳结果。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
代理获取

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号