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首页> 外文学位 >Compact gate capacitance and gate current modeling of ultra-thin (EOT ~ 1 nm and below) silicon dioxide and high-kappa gate dielectrics.
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Compact gate capacitance and gate current modeling of ultra-thin (EOT ~ 1 nm and below) silicon dioxide and high-kappa gate dielectrics.

机译：紧凑的栅极电容和栅极电流建模，可用于超薄（EOT〜1 nm及以下）二氧化硅和高kappa栅极电介质。

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摘要

The Metal-Oxide-Silicon (MOS) gate dielectrics have to be scaled down to about 1 nm to 0.5 nm equivalent oxide thicknesses (EOTs) to maintain the projected gate control over the silicon channel for ultra-large-scale-integrated (ULSI) circuits in the next generation. Various high-dielectric-constant (high-kappa) materials and metal gate electrodes are being studied heavily as the replacements for conventional SiO2 dielectrics and polysilicon gate electrode to overcome the increasingly deleterious gate leakage current and polysilicon related problems (polydepletion effects, B penetration, etc.) in conventional MOS devices. Furthermore, quantum mechanical (QM) effects and Fermi-Dirac statistics in both the Si substrate (subband formation, wave function penetration effects, etc.) and gate dielectrics (direct and Fowler-Nordheim (F-N) tunneling effects) have to be fully understood and simulated to interpret the measured gate capacitance (Cg-Vg) and gate current (Ig-Vg) behavior precisely. Although such behavior can be somewhat addressed in numerical studies of gate stacks, the increasing physical complexity of the problem has made it difficult to create compact models applicable to and below ∼1 nm EOTs. And while such numerical Cg-Vg and I g-Vg simulators can provide a physically accurate and comprehensive understanding of these effects, efficient analytic Cg-Vg and Ig-Vg models with similar accuracy are required for practical every-day device and ULSI circuit simulations. In this work, a computationally efficient and accurate physically-based integrated gate capacitance and gate current model of MOS devices with advanced ultra-thin EOT oxides (down to ∼0.5 nm) is introduced for current and future integrated circuit technology nodes. With the aid of self-consistent numerical Schrodinger-Poisson calculations, the QM effects have been reconsidered in this model. The 2/3 power law for the lowest quantized energy level versus field relations (E1 ∝ Fox2/3), often used in compact models, was refined to 0.61 for electrons and 0.64 for holes, respectively, in the substrate in the regimes of moderate to strong inversion and accumulation to address primarily barrier penetration more accurately. The filling of excited states consistent with Fermi-Dirac statistics has been addressed. Within the same framework for surface potential and available carriers for tunneling, a modified version of the conventional Wentzel-Kramers-Brillouin (WKB) approximation allows for the effects of the abrupt material interfaces and non-parabolicities in complex bandstructures of the individual dielectrics on the tunneling current (both direct and F-N). The model was implemented and tested by comparisons to both numerical calculations down to 0.5 nm, and to experimental data from n-MOS or p-MOS metal-gate devices with SiO2, Si3N 4 and high-kappa (e.g., HfO2) gate dielectrics on (100) Si with EOTs down to ∼1 nm. The compact model has also been adapted to address interface states, and poly-depletion and poly-accumulation effects on gate capacitance. A nonlinear least-square fitting program is demonstrated for fast and automatic gate characterization and parameter extraction for the 45-nm CMOS technology node and beyond.
机译：金属氧化物硅（MOS）栅极电介质必须缩小至约1 nm至0.5 nm等效氧化物厚度（EOT），以维持对硅沟道的投影栅极控制，以实现超大规模集成（ULSI）下一代电路。各种高介电常数（高κ）材料和金属栅电极正在作为替代传统的SiO2电介质和多晶硅栅电极的替代材料，以克服日益严重的栅漏电流和与多晶硅相关的问题（多晶硅耗尽效应，B穿透，等）。此外，必须充分了解Si衬底（子带形成，波函数穿透效应等）和栅极电介质（直接和Fowler-Nordheim（FN）隧穿效应）中的量子力学（QM）效应和费米-狄拉克统计量。并进行仿真以精确解释测得的栅极电容（Cg-Vg）和栅极电流（Ig-Vg）行为。尽管这种行为可以在门叠层的数值研究中得到解决，但问题的物理复杂性不断提高，难以创建适用于1 nm以下EOT的紧凑模型。尽管此类数值Cg-Vg和I g-Vg仿真器可以提供对这些影响的物理准确和全面的理解，但实际的日常设备和ULSI电路仿真仍需要具有相似精度的高效分析Cg-Vg和Ig-Vg模型。 。在这项工作中，针对当前和未来的集成电路技术节点，介绍了具有先进的超薄EOT氧化物（低至〜0.5 nm）的MOS器件的计算有效且准确的基于物理的集成栅极电容和栅极电流模型。借助自洽的Schrodinger-Poisson数值计算，已在此模型中重新考虑了质量管理效应。通常在紧凑模型中使用的最低能级与场关系（E1 ∝ Fox2 / 3）的2/3幂定律在中度条件下被分别精化为电子的0.61和空穴的0.64。强大的反演和积累，以更准确地解决主要的屏障渗透问题已经解决了与费米-狄拉克统计一致的激发态的填充。在相同的表面电势框架和可用的隧穿载流子框架内，常规Wentzel-Kramers-Brillouin（WKB）近似的改进版本允许突变的材料界面和单个电介质复杂带结构中的非抛物线效应对材料产生影响。隧道电流（直流和FN）。通过与低至0.5 nm的数值计算以及具有SiO2，Si3N 4和高kappa（例如HfO2）栅极电介质的n-MOS或p-MOS金属栅极器件的实验数据进行比较，对模型进行了实施和测试。 （100）硅的EOT降至约1 nm。紧凑型模型还适用于解决接口状态以及对栅极电容的多晶硅耗尽和多晶硅累积效应。演示了一种非线性最小二乘拟合程序，可用于45 nm CMOS技术节点及以后的节点的快速自动栅极表征和参数提取。

著录项

  • 作者

    Li, Fei.;

  • 作者单位

    The University of Texas at Austin.;

  • 授予单位 The University of Texas at Austin.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2006
  • 页码 134 p.
  • 总页数 134
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 无线电电子学、电信技术;
  • 关键词

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