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Increasing rendering performance of graphics hardware.

机译：提高图形硬件的渲染性能。

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摘要

Graphics Processing Unit (GPU) performance is increasing faster than central processing unit (CPU) performance. This growth is driven by performance improvements that can be divided into the following three categories: algorithmic improvements, architectural improvements, and circuit-level improvements. In this dissertation I present techniques that improve the rendering performance of graphics hardware measured in speed, power consumption or image quality in each of these three areas.; At the algorithmic level, I introduce a method for using graphics hardware to rapidly and efficiently generate summed-area tables, which are data structures that hold pre-computed two-dimensional integrals of subsets of a given image, and present several novel rendering techniques that take advantage of summed-area tables to produce dynamic, high-quality images at interactive frame rates. These techniques improve the visual quality of images rendered on current commodity GPUs without requiring modifications to the underlying hardware or architecture.; At the architectural level, I propose modifications to the architecture of current GPUs that add conditional streaming capabilities. I describe a novel GPU-based ray-tracing algorithm that takes advantage of conditional output streams to reduce the memory bandwidth requirements by over an order of magnitude times when compared to previous techniques.; At the circuit level, I propose a compute-on-demand paradigm for the design of high-speed and energy-efficient graphics components. The goal of the compute-on-demand paradigm is to only perform computation at the bit-level when needed. The compute-on-demand paradigm exploits the data-dependent nature of computation, and thereby obtains speed and energy improvements by optimizing designs for the common case. This approach is illustrated with the design of a high-speed Z-comparator that is implemented using asynchronous logic. Asynchronous or "clockless" circuits were chosen for my implementations since they allow for data-dependent completion times and reduced power consumption by disabling inactive components. The resulting circuit-level implementation runs over 1.5 times faster while on dissipating 25% the energy of a comparable synchronous comparator for the average case.; Also at the circuit-level, I introduce a novel implementation of counterflow pipelining, which allows two streams of data to flow in opposite directions within the same pipeline without the need for complex arbitration. The advantages of this implementation are demonstrated by the design of a high-speed asynchronous Booth multiplier. While both the comparator and the multiplier are useful components of a graphics pipeline, the objective of this work was to propose the new design paradigm as a promising alternative to current graphics hardware design practices.
机译：图形处理单元（GPU）的性能增长快于中央处理单元（CPU）的性能。这种增长是由性能改进驱动的，该性能改进可分为以下三类：算法改进，体系结构改进和电路级改进。在这篇论文中，我提出了在这三个区域中的每一个领域中提高速度，功耗或图像质量的图形硬件渲染性能的技术。在算法级别，我介绍了一种使用图形硬件快速有效地生成求和区域表的方法，求和区域表是保存给定图像子集的预先计算的二维积分的数据结构，并介绍了几种新颖的渲染技术利用求和区域表以交互帧速率生成动态，高质量的图像。这些技术提高了在当前商用GPU上渲染图像的视觉质量，而无需修改底层硬件或体系结构。在体系结构级别，我建议对当前GPU的体系结构进行修改，以增加条件流功能。我描述了一种新颖的基于GPU的光线跟踪算法，与以前的技术相比，该算法利用条件输出流将内存带宽需求降低了一个数量级以上。在电路级，我提出了一种按需计算的范例，用于设计高速，节能的图形组件。按需计算范例的目标是仅在需要时才在位级别执行计算。按需计算范例利用了与数据相关的计算性质，从而通过针对常见情况优化设计来获得速度和能耗的提高。通过使用异步逻辑实现的高速Z比较器的设计说明了这种方法。在我的实现中选择了异步或“无时钟”电路，因为它们允许依赖于数据的完成时间并通过禁用不活动的组件来降低功耗。所得到的电路级实施速度快了1.5倍，而在一般情况下，其功耗却是可比的同步比较器的25％。同样在电路级别，我介绍了一种新的逆流流水线实现，它允许两条数据流在同一流水线内沿相反方向流动，而无需进行复杂的仲裁。高速异步布斯乘法器的设计证明了这种实现方式的优势。尽管比较器和乘法器都是图形流水线的有用组成部分，但这项工作的目的是提出新的设计范例，以作为当前图形硬件设计实践的有希望的替代方法。

著录项

  • 作者

    Hensley, Justin.;

  • 作者单位

    The University of North Carolina at Chapel Hill.;

  • 授予单位 The University of North Carolina at Chapel Hill.;
  • 学科 Computer Science.
  • 学位 Ph.D.
  • 年度 2007
  • 页码 125 p.
  • 总页数 125
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 自动化技术、计算机技术;
  • 关键词

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