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Enhanced integrability of porous low-permittivity dielectrics for improved reliability in copper-based interconnects.

机译：多孔低介电常数电介质的增强的可集成性，以提高铜基互连中的可靠性。

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摘要

Achieving the aggressive device performance metrics demanded by the microelectronics industry dictates the use of low dielectric constant ('low-k') insulating materials to reduce the capacitive component of the interconnect-related RC signal propagation delay. In particular, to meet interconnect performance requirements for the 65 nm node and beyond, one approach is to introduce significant levels of porosity into the interlayer dielectric (ILD) films. However, the incorporation of porosity leads to a number of integration challenges, including increased reliability issues due to the open pores distributed on the sidewalls of vias/trenches. The research discussed in this paper demonstrates that it is possible to 'seal' the sidewalls of patterned porous dielectric layers using a specially designed deposition-etch passivation process. The concept of the process is to employ selected organosilcon precursors to deposit fully dense carbon-doped oxide (CDO) type films using plasma enhanced chemical vapor deposition (PECVD) on patterned porous dielectric structures, and then to preferentially plasma etch the material built up on the via floor. In order to ensure sufficient sealing results, several deposition-etch cycles are required.;Based on this concept, a systematic process development project was carried out. The properties of the resulting CDO films are discussed. The integration characteristics of the CDO film with candidate porous low-k material and with a subsequently deposited TaN barrier layer were also investigated. In addition, two unique approaches have been developed for the characterization of the sealing effectiveness of the cycled passivation process. These two approaches are based on spectroscopic ellipsometry and capacitance-voltage techniques. Both use the exposure of the passivated porous material to the vapor of an organic solvent to evaluate the responses of samples to the presence of the solvent vapor. Results from these experiments confirmed that the samples treated using a PECVD CDO-based passivation process were significantly less susceptible to the solvent vapor, indicating that the process developed in this work is a potential solution for dielectric pore sealing applications.
机译：要达到微电子行业所要求的积极的设备性能指标，就必须使用低介电常数（low-k）绝缘材料来减少与互连相关的RC信号传播延迟的电容成分。特别是，为了满足65 nm节点及以后节点对互连性能的要求，一种方法是在层间电介质（ILD）膜中引入大量孔隙。然而，孔隙的引入导致许多集成挑战，包括由于分布在通孔/沟槽的侧壁上的开放孔而增加的可靠性问题。本文讨论的研究表明，可以使用专门设计的沉积蚀刻钝化工艺来“密封”图案化多孔介电层的侧壁。该工艺的概念是采用选定的有机硅前驱物，通过在图案化的多孔介电结构上进行等离子增强化学气相沉积（PECVD）来沉积完全致密的碳掺杂氧化物（CDO）型薄膜，然后优先进行等离子蚀刻在其上沉积的材料过孔层。为了确保足够的密封效果，需要几个沉积-蚀刻循环。；基于该概念，进行了系统的工艺开发项目。讨论了所得CDO膜的性能。还研究了CDO膜与候选多孔低k材料以及随后沉积的TaN势垒层的集成特性。此外，已开发出两种独特的方法来表征循环钝化工艺的密封效果。这两种方法基于光谱椭圆偏振法和电容电压技术。两者都使用钝化的多孔材料暴露于有机溶剂的蒸气中以评估样品对溶剂蒸气的存在的响应。这些实验的结果证实，使用基于PECVD CDO的钝化工艺处理的样品对溶剂蒸气的敏感性显着降低，这表明这项工作开发的工艺是介电孔密封应用的潜在解决方案。

著录项

  • 作者

    Luo, Fu.;

  • 作者单位

    State University of New York at Albany.;

  • 授予单位 State University of New York at Albany.;
  • 学科 Engineering Electronics and Electrical.;Engineering Materials Science.
  • 学位 Ph.D.
  • 年度 2006
  • 页码 195 p.
  • 总页数 195
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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