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首页> 外文学位 >A table look-up pipelined multiplication-accumulation co-processor for H.264, and, An intellectual property authentication scheme for FPGA through watermarking techniques.
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A table look-up pipelined multiplication-accumulation co-processor for H.264, and, An intellectual property authentication scheme for FPGA through watermarking techniques.

机译：用于H.264的查表流水线乘法累加协处理器，以及通过水印技术用于FPGA的知识产权认证方案。

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摘要

A newly developed video standard, H.264/AVC, provides significantly better bit compression ratio and transmission efficiency. To achieve this, much higher computation power is needed. The hybrid CPU/field-programmable gate array (FPGA) chip model contains CPU (DSP) and FPGAs that can be used to reduce design cost and still support significant hardware customization. A H.264 Codec is to be implemented by a high end CPU (RM9000) and two FPGA implemented co-processors. In this thesis, we present a Table Look-Up Pipelined Multiplication-Accumulation Co-processor (MAC) for H.264 Codec, which can be used for a large number of computations in H.264 where one of the multiplicands is a constant. The proposed design is based on the pre-computed tables which generate the partial products and a three-level pipelined architecture. A design simulation with SystemC is conducted to verify functional correctness. A field programmable gate array (FPGA) implementation of MAC with Xilinx FPGA is explored. The result shows that the proposed MAC out performs the conventional multiply-accumulate unit both in size and speed.; This thesis also presents an intellectual property (IP) protection authentication scheme for FPGA with embedded watermark. Watermarking implements IP protection by making untraceable unauthorized reuse as difficult as recreating given pieces of IP from scratch. The authentication process in the proposed scheme is based on creating a watermark by encrypting the signature of the IP user with the unique FPGA board ID, which guarantees that a watermarked FPGA design can only be used on an authorized FPGA board. This could prevent the unauthorized reuses when certain users violate the copyright protection law and resell the watermarked FPGA design with signature to others.
机译：新开发的视频标准H.264 / AVC提供了明显更好的比特压缩率和传输效率。为了实现这一点，需要更高的计算能力。混合CPU /现场可编程门阵列（FPGA）芯片模型包含CPU（DSP）和FPGA，可用于降低设计成本并仍然支持大量的硬件定制。 H.264编解码器将由高端CPU（RM9000）和两个FPGA实现的协处理器实现。在本文中，我们提出了一种用于H.264编解码器的表查找流水线式乘法累加协处理器（MAC），该算法可用于H.264中被乘数之一为常数的大量计算。提议的设计基于生成部分乘积的预计算表和三级流水线体系结构。用SystemC进行设计仿真以验证功能的正确性。探索了使用Xilinx FPGA实现MAC的现场可编程门阵列（FPGA）实现。结果表明，所提出的MAC out在大小和速度上都可以执行传统的乘法累加单元。本文还提出了一种具有嵌入式水印的FPGA的IP保护认证方案。水印通过使难以追踪的未经授权的重用与从头开始创建给定IP片段一样困难而实现了IP保护。提出的方案中的认证过程基于通过使用唯一的FPGA板ID加密IP用户的签名来创建水印，这保证了带水印的FPGA设计只能在授权的FPGA板上使用。当某些用户违反版权保护法并以其他人的签名转售带有水印的FPGA设计时，这可以防止未经授权的重用。

著录项

  • 作者

    Xiao, Xiang.;

  • 作者单位

    The University of Regina (Canada).;

  • 授予单位 The University of Regina (Canada).;
  • 学科 Computer Science.
  • 学位 M.Sc.
  • 年度 2006
  • 页码 91 p.
  • 总页数 91
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 自动化技术、计算机技术;
  • 关键词

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