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Design and integration of a single-chip CMOS transceiver for passive UHF RFID readers.

机译：用于无源UHF RFID阅读器的单芯片CMOS收发器的设计和集成。

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摘要

In this thesis, a single-chip CMOS UHF RFID reader is implemented for passive RFID systems operated in 860MHz to 960MHz, which integrates a RF transceiver including IQ data converters and digital baseband.;Firstly, the distinctive features of RFID systems are analyzed, system and building block specifications are derived based on the EPCglobal Gen-2 standard. It is revealed that key challenges in implementing the RFID reader are self-interference caused by simultaneous transmitting and receiving at the same carrier frequency, as well as reconfigurability for multi-protocol operation. The goal of this project is to build systems that support multiple standards with multiple data rates and multiple modulation formats in different electromagnetic environment by a flexible system architecture.;As one of the critical building blocks, a low power low phase noise fractional-N frequency synthesizer is proposed. By properly distributing the capacitance between drain and source of a transformer-feedback VCO, the modified VCO exhibits enhancement in tank Q factor, as well as benefits from the noise filtering of even harmonics. A 3rd order 2-bit single-loop SigmaDelta modulator is optimized for the proposed synthesizer so that it achieves the optimization of phase noise and power consumption at the architecture level. In addition, the detailed design consideration, circuit implementation and theoretical analysis for a power-optimized reconfigurable baseband are presented, which is crucial for a multi-protocol RFID reader. It allows power optimization for different system bandwidth and interference scenarios.;Fabricated in 0.18mum CMOS technology, the proposed RFID reader occupies a chip area of 18.8mm2. The synthesizer achieves the phase noise of --76dBc/Hz in-band and --126dBc/Hz at 1-MHz offset with a reference spur of --84dBc. For the listen mode operation with LNA turned on, the RX front-end measures P-1dB of --9.4dBm and IIP3 of 0dBm. The worst-case RX sensitivity is --90dBm for an output SNR of 11dB for all the bandwidths from 80 KHz to 1 MHz. In the talk mode with LNA bypassed, the RX front-end measures P-1dB of 3.5dBm, IIP3 of 18dBm. RX sensitivity is --70dBm in the presence of --5dBm self-interferer. The TX achieves output P-1dB of 10.4dBm and sideband rejection ratio of --53.6dBc. With maximum interference rejection ability, RX baseband power can be dynamically optimized from 63mW at 640kbps to around 6.2mW at 40kbps. It corresponds to a total RX power of 105.6mW to 47.8mW. The proposed RFID reader dissipates a maximum power of 249mW when transmitting maximum output power of 10.4dBm and receiving the tag's response of --70dBm in the presence of --5dBm self-interferer.
机译：本文针对860MHz至960MHz的无源RFID系统实现了单芯片CMOS UHF RFID读取器，该读取器集成了包括IQ数据转换器和数字基带在内的RF收发器。并基于EPCglobal Gen-2标准推导了构建模块规范。揭示了实现RFID阅读器的主要挑战是在相同载波频率上同时发送和接收所引起的自干扰，以及多协议操作的可重新配置性。该项目的目标是通过灵活的系统架构来构建支持多种标准的系统，这些标准可在不同的电磁环境中支持多种数据速率和多种调制格式。;作为关键构建模块之一，低功耗低相位噪声分数N频率提出了合成器。通过在变压器反馈VCO的漏极和源极之间适当分配电容，改进后的VCO可以提高储能Q因子，并受益于偶次谐波的噪声过滤。针对拟议的合成器，对三阶2位单环SigmaDelta调制器进行了优化，从而在架构级别实现了相位噪声和功耗的优化。此外，还针对功率优化的可重构基带给出了详细的设计考虑，电路实现和理论分析，这对于多协议RFID读取器至关重要。它允许针对不同的系统带宽和干扰情况进行功率优化。拟议的RFID阅读器采用0.18mum CMOS技术制造，占用的芯片面积为18.8mm2。该合成器在1-MHz偏移下达到--76dBc / Hz的带内相位噪声和--126dBc / Hz的相位噪声，基准杂散为--84dBc。对于打开LNA的监听模式，RX前端测得的P-1dB为--9.4dBm，IIP3为0dBm。对于从80 KHz到1 MHz的所有带宽，输出SNR为11dB时，最坏情况下的RX灵敏度为--90dBm。在绕过LNA的通话模式下，RX前端的P-1dB为3.5dBm，IIP3为18dBm。在存在-5dBm自干扰器的情况下，RX灵敏度为-70dBm。 TX的输出P-1dB为10.4dBm，边带抑制比为-53.6dBc。凭借最大的干扰抑制能力，RX基带功率可以动态优化，从640kbps的63mW到40kbps的6.2mW左右。它对应于105.6mW至47.8mW的总RX功率。当存在-5dBm自干扰器时，建议的RFID阅读器在传输10.4dBm的最大输出功率并接收到-70dBm的标签响应时会耗散249mW的最大功率。

著录项

  • 作者

    Wang, Wenting.;

  • 作者单位

    Hong Kong University of Science and Technology (Hong Kong).;

  • 授予单位 Hong Kong University of Science and Technology (Hong Kong).;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2007
  • 页码 297 p.
  • 总页数 297
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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