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Advanced gate stacks for strained silicon devices.

机译：用于应变硅器件的高级栅极叠层。

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摘要

Due to the mobility enhancement provided by strained Si for both electrons and holes, as well as the scaling requirement and potential issues of polysilicon gate electrodes, alternative gate stacks are being pursued for strained Si devices, which warrant investigation for better understanding on the integration of high-K dielectrics and metal gate electrodes. Mobility enhancement of strained Si devices has been reported even with ultra-thin SiO2. However, additional scattering mechanisms related with high- K dielectrics and strained Si may result in mobility degradation, which requires a fundamental study. Furthermore, impacts of integration of metal gate electrodes with strained Si channels are not fully understood.; In this work, an investigation of the degradation of electrical properties of several candidate metal gate electrodes on high K dielectrics on strained Si was performed and compared with that of bulk Si samples. This work consists of three parts. Strained Si layers were grown on relaxed SiGe virtual substrates by ultrahigh vacuum rapid thermal chemical vapor deposition (UHV/RTCVD). High-K dielectrics and metal gates were formed by physical vapor deposition (PVD) methods. The first part of the study focused on the optimization of experimental conditions and the investigation of results from material analysis. The second part of this study compared electrical data from MOS capacitors fabricated with metal gate electrodes on strained Si with SiO2 as the gate dielectric with that of HfO2. Different strained Si thickness and different Ge concentration in the virtual substrate were employed to study the effects of strain and Ge out-diffusion on electrical properties. Results from strained Si MOSFETs on SiO2 or HfO2 with TaN gate electrodes achieved by standard and advanced electrical characterization, including mobility measurement, two and three level charge pumping methods, were analyzed in the last part. It was found that electrical properties degraded as the strained silicon thickness decreased, which was attributed to the presence of Ge in the strained Si layer, and more degradation was observed with SiO2 which may be due to Si consumption during oxidation. This trend of increasing degradation with decreasing strained silicon thickness did not change after rapid thermal annealing. Metal gate electrodes were found to exhibit as good performance on strained Si as on bulk Si. Strain does not lead to any degradation of the high-K/strained Si interface. Ge diffusion is the dominant cause of the Dit increase, which explains that samples with thinner strained Si films show less device performance enhancement. Less degradation with HfO2 samples was observed due to the low temperature formation process of high-K dielectrics. The mechanisms responsible for mobility degradation in strained Si devices with advanced gate stacks were discussed.
机译：由于应变硅为电子和空穴提供的迁移率增强，以及多晶硅栅电极的缩放要求和潜在问题，应变硅器件正在寻求替代栅堆叠，这有待进一步研究以更好地了解硅的集成度。高K电介质和金属栅电极。据报道，即使使用超薄SiO2，也可以提高应变硅器件的迁移率。但是，与高K电介质和应变Si相关的其他散射机制可能会导致迁移率下降，这需要进行基础研究。此外，尚未完全理解金属栅电极与应变硅沟道的集成的影响。在这项工作中，对应变硅上高K电介质上的几种候选金属栅电极的电学性能进行了研究，并将其与块状硅样品进行了比较。这项工作包括三个部分。通过超高真空快速热化学气相沉积（UHV / RTCVD），在松弛的SiGe虚拟衬底上生长应变硅层。高K电介质和金属栅极是通过物理气相沉积（PVD）方法形成的。研究的第一部分集中在优化实验条件和材料分析结果的研究上。本研究的第二部分比较了用金属栅电极在应变Si上以SiO2作为HfO2的栅电介质制造的金属栅电极的MOS数据。在虚拟衬底中使用不同的应变Si厚度和不同的Ge浓度来研究应变和Ge外扩散对电性能的影响。在最后一部分中，分析了通过标准和高级电特性（包括迁移率测量，两级和三级电荷泵浦方法）在带有TaN栅电极的SiO2或HfO2上的应变Si MOSFET的结果。已经发现，随着应变硅厚度的减小，电性能降低，这归因于应变硅层中Ge的存在，并且观察到SiO 2的更多降解，这可能是由于氧化期间的Si消耗。在快速热退火之后，随着应变硅厚度的减小，这种增加降解的趋势没有改变。发现金属栅电极在应变硅上表现出与体硅一样好的性能。应变不会导致高K /应变Si界面的任何退化。 Ge扩散是Dit增加的主要原因，这说明具有较薄应变Si膜的样品显示出较少的器件性能增强。由于高K电介质的低温形成过程，HfO2样品的降解较少。讨论了具有先进栅叠层的应变硅器件中造成迁移率降低的机理。

著录项

  • 作者

    Lin, Yanxia.;

  • 作者单位

    North Carolina State University.;

  • 授予单位 North Carolina State University.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2005
  • 页码 195 p.
  • 总页数 195
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 无线电电子学、电信技术;
  • 关键词

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