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Design approaches for signal generation circuits in nano-scaled CMOS processes.

机译：纳米级CMOS工艺中信号生成电路的设计方法。

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摘要

The Internet of Everything or Things is driving towards a densely connected wireless world where more than 30 billion devices are expected to be interconnected. These are being enabled by scaling of Complementary Metal-Oxide-Semiconductor (CMOS) technologies. However, RF circuits, in particular, voltage controlled oscillators (VCO), are still plagued by their size, frequency sensitivity to nearby circuits or materials for some applications and process variations. In this thesis, these issues are investigated and design techniques to mitigate are proposed and demonstrated.;By optimizing the design of inductor in a VCO for performance without the area constraint, and by fully filling the area underneath the inductor with other necessary components, the VCO performance including area efficiency are simultaneously improved. Exploiting this, a 4.3-5.6 GHz VCO with an area of 14,400 mum2, and FOMA and FOMTA of -202 and -210 dBc/Hz, respectively has been demonstrated in a 65-nm CMOS process. The VCO performance is further improved by using NMOS PMOS cross coupled pairs and operating at 16 to 19 GHz, which are near the frequency at which the LC tank Q the maximum in the CMOS process. The output is frequency divided by four to generate signals at 4 to 4.8 GHz. These reduce the circuit area by ∼3X. The circuit including all the components achieves FOMA and FOMTA of -209 and -215 dBc/Hz, respectively.;A measurement setup including a metal plate probe mounted on a micrometer controlled positioner is used to quantify the effects of surroundings to VCO characteristics. Including a metal-ring shield around the inductor of LC-VCO and placing components underneath the inductor to reduce the circuit area lower the sensitivity of VCO performance to surroundings. A 4.3-GHz VCO using an addressable array of cross-coupled minimum size NMOS transistor pairs for post fabrication selection is demonstrated in 65-nm CMOS. An algorithm based on Hamming distance using the phase noise measurements of ∼1,500 array combinations was used to identify combinations that have the record breaking phase noise of -130dBc/Hz at 1-MHz offset from a 4.3-GHz carrier while consuming 5.2 mW from a 1-V supply.
机译：万物互联正在朝着紧密连接的无线世界发展，该世界将互连超过300亿个设备。这些都是通过互补金属氧化物半导体（CMOS）技术的规模实现的。然而，对于某些应用和工艺变化，RF电路，特别是压控振荡器（VCO），仍然受其尺寸，对附近电路或材料的频率敏感性困扰。通过对VCO中电感器的设计进行优化以实现无面积限制的性能，并通过在电感器下面的区域完全填充其他必要的组件，可以解决这些问题，并提出并演示了缓解这些问题的设计技术。同时提高了VCO性能，包括面积效率。利用这一点，已经在65 nm CMOS工艺中证明了面积为14,400 mum2的4.3-5.6 GHz VCO，以及分别为-202和-210 dBc / Hz的FOMA和FOMTA。通过使用NMOS PMOS交叉耦合对并在16至19 GHz的频率下工作，可以进一步提高VCO性能，该频率接近LC电路Q在CMOS工艺中达到最大值的频率。输出被四分频以生成4到4.8 GHz的信号。这些将电路面积减少了约3倍。包含所有组件的电路分别实现FOMA和FOMTA分别为-209和-215 dBc / Hz。测量设置包括安装在测微控制的定位器上的金属板探头，用于量化环境对VCO特性的影响。在LC-VCO的电感器周围包括金属环屏蔽层，并在电感器下方放置组件以减小电路面积，从而降低了VCO性能对周围环境的敏感性。在65 nm CMOS中演示了使用交叉耦合的最小尺寸NMOS晶体管对的可寻址阵列进行后期制造选择的4.3 GHz VCO。一种基于汉明距离的算法，该算法使用约1,500个阵列组合的相位噪声测量值来确定组合，这些组合在从4.3 GHz载波偏移1 MHz时具有创纪录的-130dBc / Hz的破相位噪声，而从6.3 GHz载波消耗5.2 mW。 1 V电源。

著录项

  • 作者

    Jha, Amit.;

  • 作者单位

    The University of Texas at Dallas.;

  • 授予单位 The University of Texas at Dallas.;
  • 学科 Electrical engineering.
  • 学位 Ph.D.
  • 年度 2016
  • 页码 136 p.
  • 总页数 136
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 康复医学;
  • 关键词

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