• 主题
高级搜索  >
历史搜索 清空历史
首页> 外文学位 >Analysis of logic block architectures and functional improvement of fine grained cells.
【24h】

Analysis of logic block architectures and functional improvement of fine grained cells.

机译：逻辑块架构分析和细粒度单元的功能改进。

获取原文
获取原文并翻译 | 示例
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

The first objective of this research project was to evaluate the performance of various logic block architectures in FPGAs. Since logic blocks widely vary in size, functionality and complexity, we were motivated to explore them in detail. For our study, logic blocks from Actel, Altera, Quicklogic and Xilinx were chosen along with some designs discussed in the academia. These cells were either multiplexer based or look-up-table (LUT) based. Structural VHDL models of all these blocks were constructed and benchmarks circuits were mapped. Results at this stage suggested that, although the coarse grained cells occupied more area and showed poor utilization, they were considerably faster than the fine grained cells.; The second objective was to improve the performance of the Actel Proasicplus (fine grained) logic block by enhancing its functional capabilities. During this process we came up with three modified architectures. These new cells were laid out in MAGIC using a TSMC 0.18mum technology file with lambda = 0.09 mum and the extracted files were simulated in PSpice. This transistor level data helped us to estimate the area and propagation delay of the new architectures. The modified architectures were also tested for performance by implementing the previous benchmarks and a significant improvement in speed, occupied area and utilization was observed.
机译：该研究项目的首要目标是评估FPGA中各种逻辑块架构的性能。由于逻辑块的大小，功能和复杂性差异很大，因此我们有动机去详细研究它们。在我们的研究中，选择了Actel，Altera，Quicklogic和Xilinx的逻辑模块以及学术界讨论的一些设计。这些单元基于多路复用器或基于查找表（LUT）。构建了所有这些模块的结构VHDL模型，并绘制了基准电路。该阶段的结果表明，尽管粗粒细胞占据更多的面积并显示出较差的利用率，但是它们比细粒细胞快得多。第二个目标是通过增强Actel Proasicplus（细粒度）逻辑块的功能来提高其性能。在此过程中，我们提出了三种修改后的体系结构。使用TSMC 0.18mum技术文件（λ= 0.09 mum）在MAGIC中对这些新单元进行布局，并在PSpice中模拟提取的文件。该晶体管级数据帮助我们估计了新架构的面积和传播延迟。还通过实施先前的基准测试了修改后的体系结构的性能，并观察到了速度，占用面积和利用率的显着提高。

著录项

  • 作者

    Ramnath, Rohith.;

  • 作者单位

    University of Nevada, Las Vegas.;

  • 授予单位 University of Nevada, Las Vegas.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 M.S.
  • 年度 2005
  • 页码 123 p.
  • 总页数 123
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 无线电电子学、电信技术;
  • 关键词

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号