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Defect-oriented fault analysis of a two-D-flip-flop synchronizer and test method for its application.

机译：二维触发器同步器的面向缺陷的故障分析及其测试方法。

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摘要

This thesis presents defect-oriented fault modeling and analysis of a two-D-flip-flop synchronizer and provides a test method for its application circuits. Bridging (open) defects are injected into any possible pair of internal nodes of the synchronizer. Then, HSPICE is used to perform the circuit analysis of each defect. The major purpose of this analysis is to acquire all possible faults that might occur in the synchronizer by each injected bridging (open) defect. Simulation results show that bridging and open defects can cause the synchronizer to generate stuck-at fault, functional timing fault, pulse output fault, one-time pulse fault, internal oscillation fault, and undefined output fault. Moreover, fault behaviors of the synchronizer depend on the location and resistance value of each defect, the input signal pattern (rising and falling), the input signal application time, and the applied clock frequency. The issues of fault behavior under the consideration of process variation, and the relationship between defects and the synchronizer failure mechanisms are also discussed. After dealing with failure analysis, an asynchronous First-In-First-Out (FIFO) interface (for multi-clock domain circuits) as an application of the two-D-flip-flop synchronizer is implemented. The number of synchronizers in the asynchronous FIFO interface depends on the width of the address lines. A general test method for the asynchronous FIFO interface is proposed. The proposed general test method evolves to the several test methods to detect the observed faults of all synchronizers in the asynchronous FIFO interface. Programmable delay generation and calibration are used to accomplish the pseudo at-speed delay testing for the FIFO circuit. Results demonstrate that the fault modeling and test methods developed in this research are effective, and can greatly enhance the reliability of a circuit which contains multiple clock domains.
机译：本文提出了一种基于缺陷的二维触发器同步器的故障建模与分析方法，并为其应用电路提供了一种测试方法。桥接（开放）缺陷被注入到同步器的任何可能的内部节点对中。然后，使用HSPICE对每个缺陷进行电路分析。该分析的主要目的是获取由于每个注入的桥接（开路）缺陷而可能在同步器中发生的所有可能的故障。仿真结果表明，桥接和开路缺陷会导致同步器产生卡死故障，功能时序故障，脉冲输出故障，一次性脉冲故障，内部振荡故障以及不确定的输出故障。此外，同步器的故障行为取决于每个缺陷的位置和电阻值，输入信号模式（上升和下降），输入信号施加时间和施加的时钟频率。还讨论了考虑过程变化的故障行为问题，以及缺陷与同步器故障机制之间的关系。经过故障分析后，实现了一个异步先进先出（FIFO）接口（用于多时钟域电路），作为双D触发器同步器的应用。异步FIFO接口中同步器的数量取决于地址线的宽度。提出了异步FIFO接口的通用测试方法。所提出的通用测试方法演变为几种测试方法，以检测异步FIFO接口中所有同步器的观察到的故障。可编程延迟生成和校准用于完成FIFO电路的伪全速延迟测试。结果表明，本研究开发的故障建模和测试方法是有效的，并且可以大大提高包含多个时钟域的电路的可靠性。

著录项

  • 作者

    Kim, Hyoung-Kook.;

  • 作者单位

    University of Cincinnati.;

  • 授予单位 University of Cincinnati.;
  • 学科 Engineering Computer.;Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2012
  • 页码 127 p.
  • 总页数 127
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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