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首页> 外文学位 >High performance, high stability and low power SRAM design by using carbon nanotube field effect transistors.
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High performance, high stability and low power SRAM design by using carbon nanotube field effect transistors.

机译：使用碳纳米管场效应晶体管的高性能，高稳定性和低功耗SRAM设计。

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摘要

As the feature size of silicon semiconductor devices scales down to nanometer range, planar bulk CMOS design and fabrication encounter significant challenges. This situation is exacerbated when it comes to SRAM, as SRAM takes a large part of power consumption and area overhead in modern VLSI processor designs. To achieve higher performance, stability and lower power consumption, carbon nanotube (CNT) has been introduced to SRAM design as an alternative material. The semiconducting single-walled CNTs are promising candidates for the channel material of CMOS devices because of two advantages over the other semiconductor materials: high carrier mobility μ (providing high ON current, leading to high speed) and 1-D structure (providing low OFF current, leading to less leakage power).;In this research work, characterizing work of technology parameters for 6T carbon nanotube field effect transistor (CNFET) SRAM cell is performed for basic understanding of the relationship between SRAM delay/power and CNFET technology parameters. Stability issue is studied by investigating the diameter and transistor ratio impacts on the SRAM static noise margin (SNM). A stability-optimized 6T CNFET SRAM cell achieves 38.88% reading delay reduction, 21.61% writing delay reduction, 85.65% reading power reduction, 5.88% writing power reduction, 97.80% leakage power reduction, 41.41% SNM increment, 91.23% reading power-delay product (PDP) reduction and 26.23% writing PDP reduction, compared with conventional silicon MOSFET SRAM cell.;To mitigate major CNT imperfection impacts on CNFET circuits, a misalignment immune SRAM design method is proposed to eliminate CNT misalignment problem by using etching region defined in circuit layout; and a diameter variation sensing and compensating system is designed to mitigate the negative impacts of CNT diameter variation on SRAM delay and power consumption.;A hybrid silicon/CNT 4T SRAM cell design is proposed for low-power high-density cache application, which is better than conventionally used 6T SRAM in terms of power consumption and circuit area.;Finally, a design flow of high performance, high stability and low power SRAM is summarized.
机译：随着硅半导​​体器件的特征尺寸缩小到纳米范围，平面体CMOS的设计和制造面临着巨大的挑战。当涉及到SRAM时，这种情况会更加恶化，因为SRAM占用了现代VLSI处理器设计中的大部分功耗和面积开销。为了实现更高的性能，稳定性和更低的功耗，碳纳米管（CNT）已作为替代材料引入SRAM设计。由于与其他半导体材料相比，半导体单壁碳纳米管具有两个优势：高载流子迁移率μ（提供高导通电流，导致高速）和一维结构（提供低关断），因此，单壁CNTs有望成为CMOS器件沟道材料的候选材料。在本研究工作中，进行6T碳纳米管场效应晶体管（CNFET）SRAM单元技术参数的表征工作是为了基本了解SRAM延迟/功率与CNFET技术参数之间的关系。通过研究直径和晶体管比率对SRAM静态噪声容限（SNM）的影响来研究稳定性问题。经过稳定优化的6T CNFET SRAM单元实现了38.88％的读取延迟减少，21.61％的写入延迟减少，85.65％的读取功率减少，5.88％的写入功率减少，97.80％的泄漏功率减少，41.41％的SNM增量，91.23％的读取功率延迟与传统的硅MOSFET SRAM单元相比，产品（PDP）的减少和写入PDP的减少了26.23％.;为了减轻CNT对CNFET电路的主要影响，提出了一种不对准免疫SRAM设计方法，该方法通过使用在MOSFET中定义的蚀刻区域来消除CNT不对准问题。电路布局；并设计了一种直径变化传感和补偿系统，以减轻CNT直径变化对SRAM延迟和功耗的负面影响。提出了一种混合硅/ CNT 4T SRAM单元设计，用于低功率高密度高速缓存应用，在功耗和电路面积方面优于传统的6T SRAM。最后，总结了高性能，高稳定性和低功耗SRAM的设计流程。

著录项

  • 作者

    Wang, Wei.;

  • 作者单位

    Illinois Institute of Technology.;

  • 授予单位 Illinois Institute of Technology.;
  • 学科 Engineering Electronics and Electrical.;Nanotechnology.
  • 学位 Ph.D.
  • 年度 2012
  • 页码 116 p.
  • 总页数 116
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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