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Analysis and design considerations for AC coupled interconnection systems.

机译：交流耦合互连系统的分析和设计注意事项。

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摘要

As the process technologies for microelectronic integrated circuits continue to improve, both the amount of integrated, on-chip functionality and the number of required off chip interconnections (I/O) will continue to increase. These I/O will not only become more numerous but also will need to be packed densely and be capable of operating both with high bandwidth and low power. Packaging technology research is aimed at increasing I/O density and circuit research is underway to improve the bandwidth and power performance of I/Os. Advances are being made in each of these areas, but industrial roadmaps predict that these advances will not keep pace with the needed improvements. The research in this dissertation addresses this widening technological gap.;The central thesis in this work hinges on the recognition that arrays of densely packed, low-power, high-bandwidth I/Os can be created if the physical structure of each I/O is optimized for the type of information it must transmit. For example, the DC component of digital signals carries no information. Instead, digital signals contain information at frequencies well above DC (where the exact frequency spectrum of the information depends upon the edge rate of the data transitions). This can be exploited by recognizing that AC information can be transmitted across a boundary with non-contacting structures such as two plates of a capacitor or two coupled inductors. An I/O array can then be built with non-contacting structures for AC signals and direct contacts such as solder bumps only where DC signal transfers are needed. In this way, AC signal paths are freed from the mechanical constraints of direct, contacting structures and both the compliance and rework problems encountered in other high density interconnect technologies can be alleviated.;Capacitive and Inductive AC Coupled Interconnections are extensively analyzed and measured in this work and presented as a means to provide an array of sub-100mum pitched, low-power, multi-gigabit per second per pin interconnections. A packaging structure that enables AC Coupled Interconnections is also presented.
机译：随着微电子集成电路的处理技术的不断改进，集成的片上功能的数量和所需的片外互连（I / O）的数量都将继续增加。这些I / O不仅将变得越来越多，而且将需要被密集地包装，并且能够以高带宽和低功率运行。封装技术研究旨在提高I / O密度，并且正在进行电路研究以提高I / O的带宽和功率性能。这些领域都在取得进步，但是工业路线图预测，这些进步将无法与所需的改进保持同步。本论文的研究解决了这一日益扩大的技术差距。本工作的中心论点在于认识到，如果每个I / O的物理结构都可以创建密集排列，低功耗，高带宽的I / O阵列。针对必须传输的信息类型进行了优化。例如，数字信号的直流分量不携带任何信息。取而代之的是，数字信号包含的信息频率远高于DC（信息的确切频谱取决于数据转换的边沿速率）。可以通过认识到交流信息可以通过非接触结构（例如电容器的两个极板或两个耦合的电感器）通过边界传输来利用这一点。然后，仅在需要DC信号传输的地方，才能为I / O阵列构建用于AC信号和直接触点（例如焊料凸点）的非接触式结构。通过这种方式，交流信号路径摆脱了直接接触结构的机械约束，并且可以缓解其他高密度互连技术中遇到的合规性和返工问题。;电容和电感式交流耦合互连在此进行了广泛的分析和测量的工作原理，并提出了一种方法，以提供每引脚互连每秒100mM以下的节距，低功耗，几千兆位的互连。还介绍了实现交流耦合互连的封装结构。

著录项

  • 作者

    Mick, Stephen Edward.;

  • 作者单位

    North Carolina State University.;

  • 授予单位 North Carolina State University.;
  • 学科 Electrical engineering.
  • 学位 Ph.D.
  • 年度 2004
  • 页码 165 p.
  • 总页数 165
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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