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首页> 外文学位 >Assembly process development for fine pitch (0.4 mm) package-on-package devices in a lead-free assembly environment.
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Assembly process development for fine pitch (0.4 mm) package-on-package devices in a lead-free assembly environment.

机译：在无铅组装环境中开发小间距（0.4 mm）层叠封装器件的组装工艺。

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摘要

The ever increasing demand for miniaturization of electronic devices with high end functionality and larger memory capacities has driven the electronics industry to explore for novel and innovative technological solutions to satisfy the consumer needs. Increasing the circuit density on the printed circuit board (PCB) surface has reached a saturation point where circuit designers have no more real estate to accommodate devices in order to satisfy the growing consumer demands.;One of the emerging and most promising solutions is three dimensional (3D) packaging. Device manufacturers and circuit designers are now exploring innovative methods of using the space available in the 'Z' direction. The design conceptualization in 3D packaging is different from that of 2D packaging where incremental changes are made to increase the functionality and performance of the products. 3D packaging requires a new approach to logic design, package design and also considers the effect of these changes to the existing manufacturing, assembly, testing and inspection processes.;The package-on-package (PoP) technology is one of the 3D packaging techniques that is currently prevalent in the electronics industry. This technology is not new, however, most of the research work conducted in this field has been proprietary and so there are limited published resources, especially from a package assembly process perspective. This research endeavor focuses on the development of a robust and repeatable assembly process for fine pitch (0.4 mm) PoP devices in a lead free assembly environment.;This study includes validation of printing process parameters, development of placement process, identification of key equipment requirements, determination of reflow process window and assessment of the effect of reflow profile on the warpage characteristics of the PoP device. The design of experiments (DOE) approach was used in this study.;This study was able to provide a process window for the successful assembly of the PoP devices. A peak temperature range of 235°C to 250°C with a ramp rate range of 0.5°C/s to 1.25°C/s was able to form a good solder interconnection. The study also shows that a good solder joint was formed when the top package was dipped in either solder paste or flux.
机译：对具有高端功能和更大存储容量的电子设备的小型化的不断增长的需求，驱使电子工业探索新颖和创新的技术解决方案以满足消费者的需求。增加印刷电路板（PCB）表面上的电路密度已达到饱和点，电路设计人员没有更多的空间来容纳设备，以满足不断增长的消费者需求。新兴且最有前途的解决方案之一是三维（3D）包装。器件制造商和电路设计人员现在正在探索在“ Z”方向上利用可用空间的创新方法。 3D封装中的设计概念与2D封装中的设计概念不同，后者进行了增量更改以提高产品的功能和性能。 3D封装需要一种新的逻辑设计，封装设计方法，并且还要考虑这些更改对现有制造，组装，测试和检查过程的影响。;层叠封装（PoP）技术是3D封装技术之一目前在电子行业很普遍。这项技术不是新技术，但是，在该领域中进行的大多数研究工作都是专有的，因此发表的资源有限，尤其是从包装组装过程的角度来看。这项研究工作的重点是在无铅组装环境中开发用于小间距（0.4 mm）PoP器件的稳健且可重复的组装工艺。该研究包括验证印刷工艺参数，开发贴装工艺，确定关键设备要求，确定回流工艺窗口并评估回流曲线对PoP器件翘曲特性的影响。本研究使用实验设计（DOE）方法。该研究能够为PoP设备的成功组装提供一个过程窗口。 235°C至250°C的峰值温度范围和0.5°C / s至1.25°C / s的升温速率范围能够形成良好的焊料互连。研究还表明，将顶部封装浸入焊膏或助焊剂中会形成良好的焊点。

著录项

  • 作者

    Vijayanath, Vignesh.;

  • 作者单位

    State University of New York at Binghamton.;

  • 授予单位 State University of New York at Binghamton.;
  • 学科 Engineering Industrial.
  • 学位 M.S.
  • 年度 2010
  • 页码 162 p.
  • 总页数 162
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 水产、渔业;
  • 关键词

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