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Performance bound energy efficient cache organization for multi-core processors: A comparison of private and shared cache.

机译：性能受限的多核处理器的节能缓存组织：私有缓存和共享缓存的比较。

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摘要

Continuous scaling down of transistors and diminishing processor energy efficiency have led to the search of various power saving methods. While performance and power efficiency are the major advantages of the multicore versus single-processor approach, there are performance challenges as the number of cores increase. One of the potential performance issues is the memory bandwidth bottleneck. In multicore this problem can be dealt with by distributing caches along with the processors within the cores (private cache). Another problem is as the number of cores increases the average cache size per core will be decreased resulting in higher miss rates. If a shared cache is used it could be allocated based on the need to overcome this problem. Keeping these two problems in mind the energy savings through tuning a private and shared cache is explored in this research.;The full potential of multicore processors can be harnessed when the application running on them shows parallelism. Today's applications and workloads have ample parallelism and emphasis on parallel programming is increasing. Hence the performance and energy analysis is done with parallel work load on the processors.;A slow cache with high hit-rates can yield the same or better speed-up than fast caches with small hit-rates. This fact can be used to build multi-level cost efficient cache hierarchies. The target applications must be known to maximize the performance improvements through increasing cache hit rates. Also applications require highly diverse cache configurations for optimal energy consumption in the memory hierarchy. Hence various cache organizations are simulated and their performance and energy tradeoff are studied for emerging workload. Finally, the trend in performance and energy consumption for the optimized private and shared cache configurations with increasing number of cores is analyzed.
机译：晶体管的不断缩小和处理器能效的降低导致人们寻求各种节能方法。尽管性能和功率效率是多核与单处理器方法相比的主要优势，但是随着核数的增加，仍然存在性能挑战。潜在的性能问题之一是内存带宽瓶颈。在多核中，可以通过在内核中分配缓存以及处理器（专用缓存）来解决此问题。另一个问题是，随着内核数量的增加，每个内核的平均缓存大小将减少，从而导致更高的未命中率。如果使用共享缓存，则可以根据克服此问题的需要进行分配。在本研究中，我们牢记了这两个问题，即通过调整私有和共享缓存来节省能源。当运行在多核处理器上的应用程序显示并行性时，可以利用多核处理器的全部潜力。当今的应用程序和工作负载具有足够的并行性，并且对并行编程的重视程度日益提高。因此，性能和能量分析是通过处理器上的并行工作负载完成的。具有高命中率的慢速缓存可以比具有低命中率的快速缓存产生相同或更好的加速。此事实可用于构建多级成本有效的缓存层次结构。必须知道目标应用程序，以通过提高缓存命中率来最大程度地提高性能。此外，应用程序还需要高度多样化的缓存配置，以在内存层次结构中实现最佳能耗。因此，模拟了各种缓存组织，并针对新兴的工作负载研究了它们的性能和能量折衷。最后，分析了随着内核数量的增加而优化的专用和共享缓存配置的性能和能耗趋势。

著录项

  • 作者

    Arun, Ramya.;

  • 作者单位

    The University of Texas at San Antonio.;

  • 授予单位 The University of Texas at San Antonio.;
  • 学科 Engineering Computer.
  • 学位 M.S.
  • 年度 2010
  • 页码 95 p.
  • 总页数 95
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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