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首页> 外文期刊>Journal of Circuits, Systems, and Computers >V-SET CACHE: AN EFFICIENT ADAPTIVE SHARED CACHE FOR MULTI-CORE PROCESSORS
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V-SET CACHE: AN EFFICIENT ADAPTIVE SHARED CACHE FOR MULTI-CORE PROCESSORS

机译：V-SET CACHE：多核处理器的有效自适应共享CACHE

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摘要

Development in VLSI design allows multi- to many-cores to be integrated on a single microprocessor chip. This increase in the core count per chip makes it more critical to design an efficient memory sub-system especially the shared last level cache (LLC). The efficient utilization of the LLC is a dominant factor to achieve the best microprocessor throughput. Conventional set-associative cache cannot cope with the new access pattern of the cache blocks in the multi-core processors. In this paper, the authors propose a new design for LLC in multi-core processor. The proposed v-set cache design allows an adaptive and dynamic utilization of the cache blocks. Unlike lately proposed design such as v-way caches, v-set cache design limits the serial access of cache blocks. In our paper, we thoroughly study the proposed design including area and power consumption as well as the performance and throughput. On eight-core microprocessor, the proposed v-set cache design can achieve a maximum speedup of 25% and 12% and an average speedup of 16% and 6% compared to conventional n-way and v-way cache designs, respectively. The area overhead of v-set does not exceed 7% compared to n-way cache.
机译：VLSI设计的开发允许在单个微处理器芯片上集成多核到多核。每个芯片内核数量的增加使得设计高效的内存子系统（尤其是共享的最后一级缓存（LLC））变得更加关键。 LLC的有效利用是实现最佳微处理器吞吐量的主要因素。常规的集合关联缓存无法应对多核处理器中缓存块的新访问模式。在本文中，作者提出了一种用于多核处理器的LLC的新设计。提出的v-set缓存设计允许缓存块的自适应和动态利用。与最近提出的诸如V路高速缓存的设计不同，V集高速缓存设计限制了对高速缓存块的串行访问。在本文中，我们彻底研究了建议的设计，包括面积和功耗以及性能和吞吐量。在八核微处理器上，与传统的n向和v向高速缓存设计相比，拟议的v-set高速缓存设计分别可以实现25％和12％的最大加速以及16％和6％的平均加速。与n路缓存相比，v集的区域开销不超过7％。

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