首页> 外文学位 >Interfacial adhesion and subcritical debonding of low-k dielectrics in flip-chip-packaged copper/low-k interconnect structures.
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Interfacial adhesion and subcritical debonding of low-k dielectrics in flip-chip-packaged copper/low-k interconnect structures.

机译:倒装芯片封装的铜/低k互连结构中低k电介质的界面粘附和亚临界剥离。

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摘要

To improve electrical performance, the semiconductor industry is adopting copper metallization and low-permittivity (low-k) dielectric for on-chip interconnect structures. However, it is currently unclear how copper/low-k implementation will impact thermomechanical reliability, particularly since many candidate low-k dielectrics are polymeric. Compared with currently used SiO2, even the most ideal low-k polymers have increased CTE, reduced strength and lower elastic modulus. In addition to generating a greater local CTE mismatch within the structure, replacing SiO2 with a more compliant dielectric may allow the interconnect structure to undergo a greater degree of deformation on a global scale, especially when packaged. When packaged in a flip-chip configuration, the interconnect structure will be subjected to the global bending of the package, driven by the large CTE mismatch between the silicon chip and organic printed circuit board (PCB).; The first objective of this study was to quantify the fracture behavior of pertinent low-k interfaces using two candidate dielectrics. To this end, the mode-I and mixed-mode critical and subcritical fracture behavior was measured for Dow Chemical's benzocyclobutene (BCB) and SiLK(TM) in various configurations with Ta, TaN, Si3N4 and SiO2.; The second goal was to determine how much energy is available to propagate an existing interfacial crack in a flip-chip package at room temperature. This was achieved experimentally through phase-shifting more interferometry (PSMI) and numerically via finite element modeling. Essentially, PSMI was used to compute the crack driving force and strain-state for an experimentally viable thermal load of -80°C. Finite element modeling was used to verify these results and extend the study to a more realistic thermal load encountered by a flip-chip package at room temperature, about -145°C. Additionally, finite element modeling was employed to examine the variation of crack driving force and mode-mixity with changes in package geometry.; Results indicate that the crack driving force is sufficient to debond BCB/Ta and BCB/TaN interfaces critically and BCB/Si3N4 interfaces subcritically. SiLK interfaces showed greater adhesion, with critical and subcritical energies exceeding the driving force by 100--1000% depending on the interface. Driving force and mode-mixity were relatively insensitive to package geometry, but very sensitive to PCB CTE and modulus.
机译:为了改善电性能,半导体行业正在采用铜金属化和低介电常数(low-k)的电介质作为片上互连结构。但是,目前尚不清楚铜/低k实施将如何影响热机械可靠性,特别是由于许多候选的低k电介质是聚合物。与目前使用的SiO2相比,即使是最理想的低k聚合物也具有提高的CTE,降低的强度和更低的弹性模量。除了在结构内产生更大的局部CTE不匹配之外,用更柔顺的电介质代替SiO2可能使互连结构在全球范围内经受更大程度的变形,尤其是在封装时。当以倒装芯片配置进行封装时,由于硅芯片与有机印刷电路板(PCB)之间的巨大CTE不匹配,互连结构将受到封装整体弯曲的影响。这项研究的第一个目标是使用两种候选电介质来量化相关低k界面的断裂行为。为此,在具有Ta,TaN,Si3N4和SiO2的各种配置下,对Dow Chemical的苯并环丁烯(BCB)和SiLKTM进行了I型和混合模式的临界和亚临界断裂行为的测量。第二个目标是确定在室温下有多少能量可用于传播倒装芯片封装中现有的界面裂纹。这是通过相移更多干涉测量法(PSMI)以及通过有限元建模在数值上通过实验实现的。本质上,对于实验上可行的-80°C热负荷,PSMI用于计算裂纹驱动力和应变状态。有限元建模用于验证这些结果,并将研究扩展到倒装芯片封装在室温(约-145°C)下遇到的更实际的热负荷。另外,采用有限元建模来检查裂纹驱动力和模式混合随包装几何形状的变化。结果表明,裂纹驱动力足以使BCB / Ta和BCB / TaN界面严重脱粘,而BCB / Si3N4界面则较亚临界。 SiLK界面显示出更大的附着力,临界和次临界能量超过驱动力100--1000%,具体取决于界面。驱动力和模式混合对封装几何形状相对不敏感,但对PCB CTE和模量非常敏感。

著录项

  • 作者

    Miller, Mikel Rolf.;

  • 作者单位

    The University of Texas at Austin.;

  • 授予单位 The University of Texas at Austin.;
  • 学科 Engineering Materials Science.; Engineering Mechanical.
  • 学位 Ph.D.
  • 年度 2000
  • 页码 170 p.
  • 总页数 170
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 工程材料学;机械、仪表工业;
  • 关键词

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