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首页> 外文学位 >Physics and technology of low temperature germanium MOSFETs for monolithic three dimensional integrated circuits.
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Physics and technology of low temperature germanium MOSFETs for monolithic three dimensional integrated circuits.

机译：单片三维集成电路的低温锗MOSFET的物理和技术。

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摘要

As the minimum feature size of silicon (Si) CMOS devices shrinks to the nanometer regime, device behavior becomes increasingly complex, due to new physical phenomena at short dimensions and fundamental limitations in material properties are reached. One of the techniques that shows promise to overcome this obstacle is the utilization of monolithic three-dimensional integrated circuits (3D-ICs). By stacking devices vertically, it is expected that (1) more functionality can fit into a smaller space and (2) the signal delay and power consumption in the interconnect layers will decrease and bandwidth will increase. The major challenge in fabricating monolithic 3D-ICs is the maximum process temperature limit of 400°C in the upper layers of CMOS device processing, due to the fact that higher process temperature would destroy the underlying device and interconnect layers. (1) Single crystalline GeOI growth technique at below 360°C. First, we have investigated Ni or Au-induced crystallization and lateral crystallization of planar amorphous germanium (alpha-Ge) on SiO2 at 360°C without the deleterious effects of thermally induced self-nucleation. Subsequently, single crystalline Ge growth has been achieved on SiO2 by making dimension of alpha-Ge line smaller than the size of grains formed using Ni and Au-induced lateral crystallization at 360°C. (2) Low temperature dopants activation technique in Ge. Second, we have investigated low temperature boron and phosphorus activation in alpha-Ge using the metal-induced crystallization technique. Eight candidates of metals including Pd, Cu, Ni, Au, Co, Al, Pt, and Ti are used to crystallize alpha-Ge at low temperatures followed by resistivity measurement, TEM, and XRD analyses, thereby revealing behaviors of the metal-induced dopants activation process where metals react with alpha-Ge at a low temperature. It is found that Co achieves the highest B and P activation ratio in Ge below 360°C with slow diffusion rate. The feasibility of low temperature activation technique has been demonstrated for a Ge gate electrode in a Si P-MOSFET using Schottky Ni (or Co) silicide source/drain. (3) High performance and low temperature Ge CMOS technology. Third, we demonstrate high performance n+/p & p+/n junction diodes and N & P-channel Ge MOSFETs, where Ge is heteroepitaxially grown on a Si substrate at sub 360°C and the low temperature gate stack comprises of Al/Al2O3/GeO2. Shallow (-100 nm) source/drain junctions with very low series resistivity [5.2 x10 -4 O-cm (in n+/p junction) and 1.07 x 10 -3 O-cm (in p+/n junction) at the lowest point of SRP] and high degree of dopant activation are achieved by Co-induced dopant activation technique. Consequently, high diode and transistor current on/off ratios (∼1.1 x 104 & ∼1.13 x10 3 for N-MOSFETs and ∼2.1 x 104 & ∼1.09 x 103 for P-MOSFETs) were obtained in these N & P-channel Ge MOSFETs.;These low temperature processes can be utilized to fabricate Ge CMOS devices on upper layers in three-dimensional integrated circuits, where low temperature processing is critical.
机译：随着硅（Si）CMOS器件的最小特征尺寸缩小到纳米状态，由于行为在短尺寸上出现了新的物理现象并且达到了材料特性的基本限制，因此器件的行为变得越来越复杂。有望克服这一障碍的技术之一是利用单片三维集成电路（3D-IC）。通过垂直堆叠设备，可以预期（1）更多的功能可以放入更小的空间中；（2）互连层中的信号延迟和功耗将减少，带宽将增加。制造单片3D-IC的主要挑战是CMOS器件加工的上层的最高加工温度限制为400°C，这是因为较高的加工温度会破坏下面的器件和互连层。 （1）在360°C以下的单晶GeOI生长技术。首先，我们研究了在360°C的条件下，Ni或Au诱导的平面非晶锗（alpha-Ge）在SiO2上的结晶和横向结晶，而没有热诱导的自成核的有害影响。随后，通过使α-Ge线的尺寸小于使用Ni和Au在360°C诱导的横向结晶形成的晶粒的尺寸，可以在SiO2上实现单晶Ge的生长。 （2）Ge中的低温掺杂剂活化技术。其次，我们使用金属诱导结晶技术研究了α-Ge中的低温硼和磷活化。使用八种候选金属（包括Pd，Cu，Ni，Au，Co，Al，Pt和Ti）在低温下结晶α-Ge，然后进行电阻率测量，TEM和XRD分析，从而揭示出金属诱导的行为掺杂剂激活过程，其中金属在低温下与α-Ge反应。发现Co在低于360℃的Ge中具有最高的B和P活化率，并且具有缓慢的扩散速率。对于使用肖特基镍（或钴）硅化物源极/漏极的Si P-MOSFET中的Ge栅电极，已经证明了低温激活技术的可行性。 （3）高性能低温Ge CMOS技术。第三，我们展示了高性能n + / p和p + / n结二极管以及N和P沟道Ge MOSFET，其中Ge在低于360°C的温度下在Si衬底上异质外延生长，而低温栅极堆叠由Al / Al2O3 /二氧化锗。浅（-100 nm）源/漏结，在最低点具有非常低的串联电阻率[5.2 x10 -4 O-cm（在n + / p结中）和1.07 x 10 -3 O-cm（在p + / n结中）通过Co诱导的掺杂剂活化技术可以实现高掺杂剂活化。因此，在这些N和P沟道Ge中获得了较高的二极管和晶体管电流开/关比（对于N-MOSFET，约为1.1 x 104和〜1.13 x10 3；对于P-MOSFET，约为2.1 x 104和〜1.09 x 103）。这些低温工艺可用于在低温工艺至关重要的三维集成电路的上层上制造Ge CMOS器件。

著录项

  • 作者

    Park, Jin Hong.;

  • 作者单位

    Stanford University.;

  • 授予单位 Stanford University.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2009
  • 页码 82 p.
  • 总页数 82
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 无线电电子学、电信技术;
  • 关键词

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