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Subthreshold circuits: Design, implementation and application.

机译：亚阈值电路：设计，实施和应用。

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摘要

Digital circuits operating in the subthreshold region of the transistor are being used as an ideal option for ultra low power complementary metal-oxide-semiconductor (CMOS) design. The use of subthreshold circuit design in cryptographic systems is gaining importance as a counter measure to power analysis attacks. A power analysis attack is a non-invasive side channel attack in which the power consumption of the cryptographic system can be analyzed to retrieve the encrypted data. A number of techniques to increase the resistance to power attacks have been proposed at algorithmic and hardware levels, but these techniques suffer from large area and power overheads.;The main aim of this research is to understand the viability of implementing subthreshold systems for cryptographic applications. Standard cell libraries in subthreshold are designed and a methodology to identify the minimum energy point, aspect ratio, frequency range and operating voltage for CMOS standard cells is defined. As scalar multiplication is the fundamental operation in elliptic curve cryptographic systems, a digit-level gaussian normal basis (GNB) multiplier is implemented using the aforementioned standard cells. A similar standard-cell library is designed for the multiplier to operate in the superthreshold regime. The subthreshold and superthreshold multipliers are then subjected to a differential power analysis attack. Power performance and signal-to-noise ratio (SNR) of both these systems are compared to evaluate the usefulness of the subthreshold design. The power consumption of the subthreshold multiplier is 4.554 muW, the speed of the multiplier is 65.1 KHz and the SNR is 40 dB. The superthreshold multiplier has a power consumption of 4.005 mW, the speed of the multiplier is 330 MHz and the SNR is 200 dB. Reduced power consumption, hence reduced SNR, increases the resistance of the subthreshold multiplier against power analysis attacks.
机译：在晶体管的亚阈值区域中运行的数字电路已被用作超低功耗互补金属氧化物半导体（CMOS）设计的理想选择。作为功​​率分析攻击的对策，在密码系统中使用亚阈值电路设计正变得越来越重要。功率分析攻击是一种非侵入式侧信道攻击，其中可以分析密码系统的功耗以检索加密数据。已经在算法和硬件级别提出了许多提高抗功率攻击能力的技术，但是这些技术存在较大的面积和功率开销。该研究的主要目的是了解为密码应用实现亚阈值系统的可行性。设计了亚阈值以下的标准单元库，并定义了一种方法来识别CMOS标准单元的最小能量点，纵横比，频率范围和工作电压。由于标量乘法是椭圆曲线密码系统中的基本操作，因此使用上述标准单元来实现数字级高斯正态基数（GNB）乘法器。为乘法器设计了类似的标准单元库，使其可以在超阈值状态下运行。然后，对亚阈值乘数和超阈值乘数进行差分功率分析攻击。比较这两个系统的功率性能和信噪比（SNR），以评估亚阈值设计的有用性。亚阈值乘法器的功耗为4.554μW，乘法器的速度为65.1 KHz，SNR为40 dB。超阈值乘法器的功耗为4.005 mW，乘法器的速度为330 MHz，SNR为200 dB。降低的功耗，从而降低SNR，增加了亚阈值乘法器抵抗功耗分析攻击的能力。

著录项

  • 作者

    Kanitkar, Hrishikesh.;

  • 作者单位

    Rochester Institute of Technology.;

  • 授予单位 Rochester Institute of Technology.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 M.S.
  • 年度 2009
  • 页码 139 p.
  • 总页数 139
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 无线电电子学、电信技术;
  • 关键词

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