This thesis explores the feasibility of designing a computer using gallium arsenide very large scale integrated circuits (GaAs VLSI). The following aspects are considered: technology selection, on-chip interconnects, GaAs VLSI design techniques, microprocessor design, and high-speed testing.; General high-speed technology issues are discussed, and then GaAs and silicon technologies are compared. The Vitesse direct-coupled FET logic (DCFL) technology is outlined and found capable of supporting microprocessor design.; Alternatives for on-chip interconnects are compared: superconducting, optical, air-bridge, and conventional microstrip. SPICE simulations show reduced delay times for superconductors and air-bridges compared to normal interconnect, but superconductors have only slightly reduced interconnect delays compared to metal air-bridge interconnects with identical dimensions. Optical connections do not provide an advantage when used for on-chip interconnects because of driver and receiver delay and power consumption.; Circuit and architecture design issues in GaAs VLSI are addressed next. To maximize overall speed, the designer must be able to simultaneously optimize the system architecture, chip architecture, chip layout, circuit topology, logic gates, and devices, since all aspects are interdependent. Design for improved yield and low parasitic capacitance is important for GaAs VLSI. DCFL gate and buffer design, and their layout, are examined. Two new logic styles for DCFL are introduced: the OR gate and clocked logic, which give improved yield and speed.; To test and demonstrate DCFL design techniques, a microprocessor was designed to implement the MIPS instruction set and is designed to perform at 170 MIPS average with a 250 MHz clock. Microprocessor architecture and logic design with DCFL is examined. The design process brought out layout and design issues unique to high-speed DCFL VLSI. The VLSI design experience suggests some CAD tools for minimizing circuit delay and improving the designer's productivity.; Two GaAs VLSI chips, taken from the processor design, were implemented with DCFL: a three port, 1K bit register-file and an arithmetic and logic unit (ALU). Register-file and ALU testing open high-speed testing issues, so a DCFL fault model is presented, and design for testability is discussed. As part of this, a modified scan architecture for high-speed testing is proposed.
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