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Architecting efficiency, performance, and scalability for quantum computers.

机译：为量子计算机设计效率，性能和可伸缩性。

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摘要

This thesis addresses the design of a quantum computer (QC) architecture. Quantum error correction is a dominant factor as it is required to protect quantum bits (qubits) from decoherence. However, error correction's costs are substantial and call for a scale-up of 100X more qubits and instruction-level parallelism (ILP) on the order of 10,000 simultaneous operations per cycle. These are daunting challenges for a QC architect, who must balance demands in performance, control efficiency, and scalability of design.;Error modeling is important for designing a QC so that error correction implementations and microarchitecture designs may be evaluated for effectiveness. This thesis presents a new deterministic approach to error modeling that is on the order of 1000X faster than previous Monte Carlo error models. While the deterministic error model is memory limited, it is capable of evaluating useful problems containing on the order of a dozen logical qubits encoded in the [[7,1,3]] quantum error correcting code (QECC).;This dissertation presents a new QC processor architecture that leverages highly mobile qubits found in some QC technologies such as electron-spins on liquid helium (eSHe). The processor architecture presented here is designed to efficiently handle at least an order of magnitude more ILP than previously proposed designs, and it accommodates increasing ILP with size and latency costs scaling only linearly. Compilers are also crucial to a computer's performance and efficiency, and this dissertation describes new compiler optimizations including one that reduces hardware requirements by 25% with no performance loss.;Multiple QC processors may be organized into a tiled configuration to provide sufficient ILP across the entire QC. This dissertation proposes a new distributed block tiling strategy that distributes encoded block qubits across arrays of data tiles and offloads non-critical path error correction routines to separate ancilla tiles. This strategy reduces tile capacity requirements by over 100X with the [[21,3,5]] QECC and achieves a simulated speedup of 2.8X for the eSHe QC when compared to the traditional tiling approach.;In summary, this dissertation presents a novel QC architecture and design tools that improve performance and scalability while making efficient use of both control and qubit resources.
机译：本文讨论了量子计算机（QC）体系结构的设计。量子纠错是一个主要因素，因为它需要保护量子位（qubits）免于退相干。然而，纠错的成本是巨大的，并且要求将每个周期的10,000个同时操作的数量增加100倍以上的量子位和指令级并行性（ILP）。对于质量控制架构师而言，这些挑战是艰巨的，他们必须平衡性能，控制效率和设计可扩展性方面的要求。错误建模对于设计质量控制很重要，以便可以评估错误纠正实施和微体系结构设计的有效性。本文提出了一种新的确定性错误建模方法，该方法比以前的蒙特卡洛错误模型快1000倍。虽然确定性错误模型受内存限制，但它能够评估有用的问题，这些问题包含以[[7,1,3]]量子纠错码（QECC）编码的十几个逻辑量子位。新的QC处理器体系结构，利用了某些QC技术（例如液氦电子自旋（eSHe））中发现的高度移动的量子位。与以前提出的设计相比，此处介绍的处理器体系结构被设计为可有效处理至少多一个数量级的ILP，并且它可以随着大小和等待时间成本仅线性缩放而适应日益增长的ILP。编译器对计算机的性能和效率也至关重要，因此本文介绍了新的编译器优化，其中包括将硬件需求降低25％而不会造成性能损失的优化。多个QC处理器可以组织为分块配置，以在整个系统中提供足够的ILP质量控制。本文提出了一种新的分布式块分块策略，该策略可以将编码后的块量子比特分布在多个数据块的数组中，并卸载非关键路径纠错例程以分离辅助块。 [[21,3,5]] QECC与传统的切片方法相比，此策略将eSHe QC的切片容量要求降低了100倍以上，并实现了2.8倍的模拟加速。；总而言之，本文提出了一种新颖的方法。 QC体系结构和设计工具可提高性能和可伸缩性，同时有效利用控制和量子位资源。

著录项

  • 作者

    Chi, Eric.;

  • 作者单位

    Princeton University.;

  • 授予单位 Princeton University.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2009
  • 页码 112 p.
  • 总页数 112
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 无线电电子学、电信技术;
  • 关键词

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