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Continuous compensation of binary-weighted DAC nonlinearities in bandpass delta-sigma modulators.

机译：带通delta-sigma调制器中二进制加权DAC非线性的连续补偿。

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摘要

This thesis introduces and discusses the implementation of a novel calibration technique to compensate for DAC element mismatches in bandpass multibit delta-sigma (DeltaSigma) modulators. The compensation is accomplished in the digital domain using the output bitstream of the DeltaSigma modulator; only a minor modification to the analog portion of the DeltaSigma modulator loop is needed. The technique is compatible with binary weighted element DACs and the storage requirements for the calibrated coefficients increases only linearly with the number of quantizer bits. The calibration is performed without breaking the loop, which allows continuous tracking of environmental drifts. Furthermore, the proposed technique is shown to be also applicable to lowpass DeltaSigma modulators with minor modifications to the system.;Simulation results show a peak signal to noise ratio (SNR) of 73.9 dB after calibration for a DAC with 1% mismatches, a sinusoid input signal near 1/4 of the sampling frequency and an oversampling ratio of 14. This 73.9 dB peak SNR result represents a 26 dB improvement over the non-calibrated case and it is only 0.4 dB lower than an ideal-DAC case.;The proposed compensation technique is applied to a fourth-order DeltaSigma modulator fabricated in 0.13 mum CMOS. The peak SNR of the tested chip, without compensation, is measured at 57.3 dB. With the implemented compensation technique, the peak SNR, increases to 64.5 dB. The peak SNR after calibration drops by 1.8 dB when severe mismatch is forced on the DAC elements while the same mismatch causes the SNR to drop by 10.1 dB if no calibration is used.
机译：本文介绍并讨论了一种新颖的校准技术的实现，以补偿带通多位delta-sigma（DeltaSigma）调制器中的DAC元件失配。补偿是使用DeltaSigma调制器的输出位流在数字域中完成的；只需对DeltaSigma调制器环路的模拟部分进行较小的修改即可。该技术与二进制加权元件DAC兼容，并且校准系数的存储要求仅随着量化位数的增加而线性增加。无需中断循环即可执行校准，从而可以连续跟踪环境漂移。此外，所提出的技术还显示出也适用于对系统进行了少量修改的低通DeltaSigma调制器;仿真结果表明，对于具有1％不匹配，正弦波的DAC进行校准后，峰值信噪比（SNR）为73.9 dB输入信号接近采样频率的1/4且过采样率为14。此73.9 dB的峰值SNR结果比未校准的情况提高了26 dB，仅比理想DAC的情况低0.4 dB。提出的补偿技术被应用于以0.13微米CMOS制成的四阶DeltaSigma调制器。未经补偿的被测芯片的峰值SNR为57.3 dB。利用已实施的补偿技术，峰值SNR将增加到64.5 dB。如果在DAC元件上施加严重失配，则校准后的峰值SNR降低1.8 dB，而如果不使用校准，则相同的失配会使SNR降低10.1 dB。

著录项

  • 作者

    Gagnon, Ghyslain.;

  • 作者单位

    Carleton University (Canada).;

  • 授予单位 Carleton University (Canada).;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2009
  • 页码 194 p.
  • 总页数 194
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 无线电电子学、电信技术;
  • 关键词

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