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Efficient device simulation and power optimization techniques for novel finfet circuit design.

机译：用于新型Finfet电路设计的高效器件仿真和功率优化技术。

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摘要

Recently, multi-gate transistors have been gaining attention as an alternative to conventional metal oxide semiconductor field-effect transistors (MOSFETs). Superior gate control over the channel, smaller subthreshold leakage, and reduced susceptibility to process variations are some of the key features that give multi-gate structures a competitive edge over planar MOSFETs. Among various multi-gate structures, silicon-on-insulator (SOI) FinFETs are promising owing to their ease of fabrication. However, cost-effective large-scale fabrication, efficient device simulation, accurate device/gate level characterization, smart power optimization, and novel circuit/architectural design are few key areas that need immediate attention in order for FinFETs to gain greater popularity in this decade. This thesis first focuses on developing efficient device simulation techniques to ease characterization of FinFET devices/logic gates under process-voltage-temperature (PVT) variations. Next, it proposes several power optimization techniques enabled by different implementation styles that are unique to FinFETs.;Ideally, 3D device simulation should be done for accurate characterization of FinFET devices and logic gates, but this is impractical due to the huge CPU time required for such simulations. In this thesis, we address this issue by proposing a methodology to obtain gate underlap (LUN)-adjusted 2D models for FinFETs that very accurately track 3D device behavior. Thus, we achieve 3D simulation accuracy with 2D simulation efficiency. To the best of our knowledge, this is the first such attempt. We also show that 2D device models remain valid even under PVT variations. Though adjusted 2D models can accurately track 3D FinFET device behavior, obtaining accurate 3D FinFET structures remains a prerequisite. CPU-intensive process simulation is necessary to capture all device-related physical phenomena of a 3D FinFET. Creating a process-simulated device (PSD) structure can be seen as a one-time cost for a given technology node. However, device simulation using these 3D PSD structures is also very time-consuming. Adoption of any new device requires a thorough characterization of the device and complete logic cell library. This involves a large number of simulations under PVT variations. Whereas performing these simulations with 3D PSD structures is impractical, performing a large number of variation simulations with adjusted 2D cross-sections is also time-consuming. For the first time in this thesis, we show that the states obtained from quasi-stationary (QS) simulation of a nominal device can assist in significantly reducing simulation time of similar devices under process-voltage (PV) variations. This adjusted-assisted technique is limited to QS simulations under PV variations. Hence, in order to aid circuit designers, we also present accurate analytical models using central composite rotatable design based on response surface methodology to estimate the leakage current and delay of FinFET standard cells under PVT variations.;This thesis also proposes techniques to optimize power consumption of FinFET based circuits. FinFETs can be operated in two different modes: shorted-gate (SG) or independent-gate (IG). SG and IG FinFETs may be symmetric or asymmetric. Conventional SG/IG FinFETs are symmetric. Since asymmetric SG FinFETs have better device characteristics than asymmetric IG FinFETs, we concentrate on the former. Among asymmetric SG FinFETs, asymmetric-workfunction SG (AWSG) FinFETs are notable for their ultra-low-leakage power consumption, two orders of magnitude lower than that of symmetric SG FinFETs, but at the expense of some delay penalty. We present a delay-constrained power optimization methodology in which the negligible amount of leakage power consumed by AWSG cells plays a pivotal role. We use a higher supply voltage to reduce the delay of AWSG logic circuits so that they become delay-competitive with SG FinFET logic circuits. This does increase the dynamic power consumption. However, the reduction in leakage power is so drastic that the total power still goes down significantly. The advantage increases at higher operating temperatures. Previously, researchers have primarily explored FinFETs with asymmetry in just one parameter: AWSG, asymmetric doping SG (ADSG), asymmetric underlap SG (AUSG), and asymmetric gate-oxide IG (AOIG). Although, AWSG FinFETs have been explored in the context of both logic and memory, ADSG and AUSG FinFETs have only been explored in the context of SRAM cell design. In this thesis, for the first time, we analyze multiparameter asymmetric SG FinFETs and illustrate their potential for implementing logic gates and circuits that are both ultra-low-leakage and high-performance simultaneously. We show that logic gates and circuits based on asymmetric workfunction-underlap SG (AWUSG) FinFETs provide higher performance at much less leakage power as well as less area compared to gates/circuits based on traditional SG FinFETs.
机译：近来，多栅晶体管作为常规金属氧化物半导体场效应晶体管（MOSFET）的替代品已引起关注。关键的一些特征使多栅极结构比平面MOSFET具有竞争优势，这些优点包括对通道的出色栅极控制，较小的亚阈值泄漏以及对工艺变化的敏感性降低。在各种多栅极结构中，绝缘体上硅（SOI）FinFET由于其易于制造而备受期待。然而，具有成本效益的大规模制造，有效的器件仿真，准确的器件/栅极电平表征，智能功率优化以及新颖的电路/架构设计是很少需要立即关注的关键领域，以使FinFET在本十年中获得更大的普及。本文首先关注开发有效的器件仿真技术，以简化在工艺电压-温度（PVT）变化下FinFET器件/逻辑门的表征。接下来，它提出了几种由FinFET独有的不同实现方式实现的功率优化技术;理想情况下，应进行3D器件仿真以精确表征FinFET器件和逻辑门，但由于需要大量CPU时间，因此这是不切实际的这样的模拟。在本文中，我们通过提出一种方法来获得针对FinFET的栅极下重叠（LUN）调整后的2D模型的方法，该模型可以非常准确地跟踪3D器件的行为。因此，我们以2D仿真效率实现了3D仿真精度。就我们所知，这是第一次尝试。我们还显示，即使在PVT变化下，二维设备模型仍然有效。尽管调整后的2D模型可以准确跟踪3D FinFET器件的行为，但获得准确的3D FinFET结构仍然是前提。要捕获3D FinFET的所有与设备相关的物理现象，必须进行CPU密集型过程仿真。对于给定的技术节点，创建过程仿真设备（PSD）结构可以视为一次性成本。但是，使用这些3D PSD结构进行设备仿真也非常耗时。采用任何新设备都需要对设备进行全面的特性描述，并需要完整的逻辑单元库。这涉及PVT变化下的大量仿真。尽管使用3D PSD结构执行这些模拟是不切实际的，但是使用调整后的2D横截面执行大量的变化模拟也很耗时。本文首次展示了从标称器件的准平稳（QS）仿真获得的状态可以帮助显着减少工艺电压（PV）变化下的类似器件的仿真时间。这种调整辅助技术仅限于PV变化下的QS模拟。因此，为了帮助电路设计人员，我们还基于响应面方法，使用中央复合可旋转设计提出了精确的分析模型，以估计PVT变化下FinFET标准单元的泄漏电流和延迟。;本文还提出了优化功耗的技术基于FinFET的电路。 FinFET可以两种不同模式运行：短路栅极（SG）或独立栅极（IG）。 SG和IG FinFET可以对称或不对称。常规的SG / IG FinFET是对称的。由于非对称SG FinFET具有比非对称IG FinFET更好的器件特性，因此我们将重点放在前者上。在非对称SG FinFET中，非对称功函数SG（AWSG）FinFET以其超低泄漏功耗而著称，比对称SG FinFET的功耗低两个数量级，但以一定的延迟代价为代价。我们提出了一种延迟受限的功率优化方法，其中AWSG电池消耗的泄漏功率可忽略不计，起着举足轻重的作用。我们使用较高的电源电压来减少AWSG逻辑电路的延迟，以使它们与SG FinFET逻辑电路具有延迟竞争力。这确实增加了动态功耗。但是，泄漏功率的降低是如此之大，以至于总功率仍然大大下降。在较高的工作温度下，优点会增加。以前，研究人员主要在仅一个参数上探索具有不对称性的FinFET：AWSG，不对称掺杂SG（ADSG），不对称下重叠SG（AUSG）和不对称栅极氧化物IG（AOIG）。尽管已经在逻辑和存储器方面探索了AWSG FinFET，但仅在SRAM单元设计方面探索了ADSG和AUSG FinFET。在本文中，这是第一次，我们分析了多参数非对称SG FinFET，并说明了它们在同时实现超低泄漏和高性能的逻辑门和电路方面的潜力。我们显示，与基于传统SG FinFET的栅极/电路相比，基于非对称功函数重叠SG（AWUSG）FinFET的逻辑门和电路可提供更高的性能，且泄漏功率更低，面积也更小。

著录项

  • 作者

    Chaudhuri, Sourindra Mohan.;

  • 作者单位

    Princeton University.;

  • 授予单位 Princeton University.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2015
  • 页码 176 p.
  • 总页数 176
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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