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Grok-FPGA: Generating real on-chip knowledge for FPGA fine-grain delays using timing extraction.

机译:Grok-FPGA:使用时序提取为FPGA细粒度延迟生成真正的片上知识。

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摘要

Circuit variation is one of the biggest problems to overcome if Moore's Law is to continue. It is no longer possible to maintain an abstraction of identical devices without huge yield losses, performance penalties, and energy costs. Current techniques such as margining and grade binning are used to deal with this problem. However, they tend to be conservative, offering limited solutions that will not scale as variation increases. Conventional circuits use limited tests and statistical models to determine the margining and binning required to counteract variation. If the limited tests fail, the whole chip is discarded. On the other hand, reconfigurable circuits, such as FPGAs, can use more fine-grained, aggressive techniques that carefully choose which resources to use in order to mitigate variation. Knowing which resources to use and avoid, however, requires measurement of underlying variation.;We present Timing Extraction, a methodology that allows measurement of process variation without expensive testers nor highly invasive techniques, rather, relying only on resources already available on conventional FPGAs. It takes advantage of the fact that we can measure the delay of logic paths between any two registers. Measuring enough paths, provides the information necessary to decompose the delay of each path into individual components---essentially, forming a system of linear equations. Determining which paths to measure requires simple graph transformation algorithms applied to a representation of the FPGA circuit. Ultimately, this process decomposes the FPGA into individual components and identifies which paths to measure for computing the delay of individual components.;We apply Timing Extraction to 18 commercially available Altera Cyclone III (65 nm) FPGAs. We measure 22x28 logic clusters and the interconnect within and between cluster. Timing Extraction decomposes this region into 1,356,182 components, classified into 10 categories, requiring 2,736,556 path measurements. With an accuracy of +/-3.2 ps, our measurements reveal regional variation on the order of 50 ps, systematic variation from 30 ps to 70 ps, and random variation in the clusters with sigma=15 ps and in the interconnect with sigma=62 ps.
机译:如果要继续遵循摩尔定律,电路变化是要克服的最大问题之一。不再需要在没有大量产量损失,性能损失和能源成本的情况下维护相同设备的抽象。当前的技术(例如边距和等级合并)用于解决此问题。但是,它们往往比较保守,只提供有限的解决方案,这些解决方案不会随着变化的增加而扩展。常规电路使用有限的测试和统计模型来确定抵消变化所需的裕量和合并。如果有限的测试失败,则整个芯片将被丢弃。另一方面,诸如FPGA之类的可重配置电路可以使用更细粒度,更具攻击性的技术,这些技术会仔细选择要使用的资源以减轻变化。但是,要知道要使用和避免使用哪些资源,就需要测量潜在的变化。我们提出了“定时提取”方法,该方法可以测量过程变化,而无需昂贵的测试人员或高度侵入性的技术,而仅依赖于常规FPGA上已有的资源。利用这一事实,我们可以测量任意两个寄存器之间的逻辑路径延迟。测量足够的路径可提供将每条路径的延迟分解成各个分量所必需的信息-本质上就是形成线性方程组。确定要测量的路径需要将简单的图形转换算法应用于FPGA电路的表示。最终,该过程将FPGA分解为单个组件,并确定用于计算单个组件延迟的测量路径。我们将定时提取应用于18个市售的Altera Cyclone III(65 nm)FPGA。我们测量22x28逻辑集群以及集群内部和集群之间的互连。定时提取将该区域分解为1,356,182个组件,分为10类,需要进行2,736,556个路径测量。以+/- 3.2 ps的精度,我们的测量揭示了区域变化大约为50 ps,系统变化从30 ps到70 ps,以及在sigma = 15 ps的群集中以及在sigma = 62的互连中的随机变化。 ps。

著录项

  • 作者

    Gojman, Benjamin.;

  • 作者单位

    University of Pennsylvania.;

  • 授予单位 University of Pennsylvania.;
  • 学科 Computer engineering.;Electrical engineering.;Computer science.
  • 学位 Ph.D.
  • 年度 2014
  • 页码 157 p.
  • 总页数 157
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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