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Injection Locked Synchronous Oscillators (SOs) and Reference Injected Phase-Locked Loops (PLL-RIs)

机译：注入锁定同步振荡器（SO）和参考注入锁相环（PLL-RI）

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摘要

Synchronization plays an important and fundamental role as the timing basis in digital, analog, and RF integrated circuits (ICs), where Phase-Locked Loops (PLLs) find their versatile applications. The noise sources in a traditional PLL are mainly divided into two groups: noise before the low-pass loop filter such as the noise in the reference signal, Frequency Divider (FD), Phase Frequency Detector/Charge Pump (PFD/CP); and noise after the filter such as the Voltage Controlled Oscillator (VCO) noise and the loop filter noise. The output phase noise of the PLL is the combined contribution from these two equally important in-band and out-band noise sources. This research studies the effect of the synchronization in the PLL on the decoupling of the 3dB bandwidths for different noise sources to achieve an optimum phase noise and improved locking behavior with an attenuated reference signal injection (RI) into a ring-type delay-line Voltage Controlled Synchronous Oscillator (VCSO).;This dissertation begins with the development of a generalized phase model for both LC-type and ring-type VCSOs. Next, the relationship between the device baseband noise (flicker and thermal noise) and a ring-type oscillator's phase noise is derived. In addition, noise shaping functions are introduced to describe signal injection into the VCSO to achieve suppression of the oscillator in-band phase noise. Then, the transient and steady-state behavior of a Charge-Pump PLL-RI are explained with nonlinear differential equations and the phase-plane method. The nonlinear phase equation is linearized for the small-signal condition and the s-domain noise transfer functions as well as noise bandwidths are derived for different noise sources in the major components of the PLL-RI. The effect of the loop parameters and the injection strength on the output phase noise, loop settling time, and lock in range is analyzed. The analysis is verified by the SPICE simulation and experimental results from a Charge-Pump PLL-RI using a 1GHz VCSO in GlobalFoundries 130nm standard CMOS technology.;The designed VCSO occupies a core area of 0.005 mm2, and operates from 0.5GHz to 1.7GHz. The PLL-RI, for first-harmonic locking applications, has a core area of 0.02 mm2 and consumes 2.6mW power. When a 30dB attenuation is applied, phase noise at 1MHz and 10MHz offset are reduced from -118.8dBc/Hz (PLL) to -121.9dBc/Hz (PLL-RI), and -102.3dBc/Hz (PLL) to -128.3dBc/Hz (PLL-RI), respectively, with an integrated RMS jitter from 10KHz to 30MHz of 1.55ps. Finally, another application of the PLL-RI as an integer-N frequency synthesizer is studied and tested. The PLL-RI based frequency synthesizer with the ring-type VCSO achieves comparable noise performance with LC type PLLs, but uses a much smaller chip area and features lower power consumption.;To summarize, this dissertation has throughly evaluated an oscillator and a PLL under small signal injection. Compared with the traditional PLL, the all-CMOS PLL-RI offers faster settling time, wider lock in range, and ability to decouple 3dB bandwidths for different noise sources to achieve an optimum noise performance. The applications of PLL-RIs can be extended to analog, digital, and RF systems for different timing schemes.
机译：同步在数字，模拟和RF集成电路（IC）的时序基础中起着重要的基本作用，在这些集成电路中锁相环（PLL）可以找到其通用的应用。传统PLL中的噪声源主要分为两类：低通环路滤波器之前的噪声，例如参考信号中的噪声，分频器（FD），相频检测器/电荷泵（PFD / CP）；低通滤波器。滤波器之后的噪声，例如压控振荡器（VCO）噪声和环路滤波器噪声。 PLL的输出相位噪声是这两个同等重要的带内和带外噪声源的综合贡献。这项研究研究了PLL同步对不同噪声源3dB带宽去耦的影响，以实现最佳相位噪声并通过将衰减参考信号（RI）注入环形延迟线电压来改善锁定性能受控同步振荡器（VCSO）。本文从LC型和环形VCSO通用相位模型的开发开始。接下来，得出器件基带噪声（闪烁和热噪声）与环形振荡器的相位噪声之间的关系。此外，引入了噪声整形功能来描述将信号注入VCSO以实现对振荡器带内相位噪声的抑制。然后，利用非线性微分方程和相平面法解释了电荷泵PLL-RI的瞬态和稳态行为。对于小信号条件，非线性相位方程被线性化，并且针对PLL-RI的主要组件中的不同噪声源，得出了s域噪声传递函数以及噪声带宽。分析了环路参数和注入强度对输出相位噪声，环路建立时间和锁定范围的影响。该分析通过SPICE仿真和在GlobalFoundries 130nm标准CMOS技术中使用1GHz VCSO的电荷泵PLL-RI的实验结果进行了验证;所设计的VCSO占用0.005 mm2的核心面积，工作频率范围为0.5GHz至1.7GHz 。用于初次谐波锁定应用的PLL-RI的核心面积为0.02 mm2，功耗为2.6mW。当施加30dB衰减时，在1MHz和10MHz偏移处的相位噪声从-118.8dBc / Hz（PLL）降低到-121.9dBc / Hz（PLL-RI），并且从-102.3dBc / Hz（PLL）降低到-128.3dBc / Hz（PLL-RI），具有从10KHz到30MHz的集成RMS抖动1.55ps。最后，研究并测试了PLL-RI作为整数N频率合成器的另一种应用。带有环形VCSO的基于PLL-RI的频率合成器可实现与LC型PLL相当的噪声性能，但占用的芯片面积小得多且功耗更低。总而言之，本文全面评估了振荡器和PLL小信号注入。与传统PLL相比，全CMOS PLL-RI提供了更快的建立时间，更宽的锁定范围，并能够为不同的噪声源解耦3dB带宽，以实现最佳的噪声性能。 PLL-RI的应用可以扩展到适用于不同时序方案的模拟，数字和RF系统。

著录项

  • 作者

    Lei, Feiran.;

  • 作者单位

    The Ohio State University.;

  • 授予单位 The Ohio State University.;
  • 学科 Electrical engineering.
  • 学位 Ph.D.
  • 年度 2017
  • 页码 201 p.
  • 总页数 201
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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