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Mapping and scheduling hardware tasks on the high-performance reconfigurable architectures.

机译：在高性能可重配置架构上映射和调度硬件任务。

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摘要

High-Performance Reconfigurable Computers (HPRCs) are traditional High-Performance Computers (HPCs) augmented with reconfigurable hardware co-processors, typically based on Field-Programmable Gate Arrays (FPGAs). HPRCs are capable of providing significant performance improvements for many scientific and engineering applications. Executing a hardware task graph on an FPGA consists of two steps. The first step, mapping step, is to select proper hardware implementation for each task if multiple implementation variants are available. The second step is to schedule hardware tasks into multiple FPGA configurations in an efficient way. This research investigates hardware task mapping and scheduling optimization mechanisms for HPRC systems for improved performance.;In this research, a hardware task scheduling technique, known Reduced Data Movement Scheduling (RDMS), is proposed to maximize the performance under real-life constraints. RDMS schedules hardware tasks into the least number of configurations and significantly reduces inter-configuration communication. Furthermore, RDMS leverages the data dependency among the tasks to form longer pipelines in order to improve the throughput of each single configuration. Compared with existing scheduling approaches, RDMS was shown to reduce inter-configuration communication by up to 46% based on simulation using randomly generated data flow graphs. The practicality and efficiency of the proposed algorithm were demonstrated by emulating a task graph from a real-life application, N-body simulation, under realistic constraints for bandwidth and FPGA parameters from existing HPRCs including Cray XD1 and SRC-6.;Additional improvement was introduced by incorporating a hardware library of architectural variants. Multiple implementation variants for the same hardware task enabled tradeoffs between the hardware resources consumed and the task execution throughput. A genetic algorithm (GA)-based mapping approach is developed to find the near-optimal solution, i.e., combination of task implementations, in a reasonable time. Each chromosome represents a possible mapping between hardware tasks and their implementation variants. Actual numbers for the architectural constraints, such as interconnect bandwidth and reconfiguration time, are used from three different reconfigurable platforms - SGI RC100, SRC-6 and Cray XD1. The results demonstrated improvements of up to 78.6% in the execution time, compared with choosing a fixed implementation variant for each task.
机译：高性能可重新配置计算机（HPRC）是传统的高性能计算机（HPC），其通常基于现场可编程门阵列（FPGA）加上可重新配置的硬件协处理器。 HPRC能够为许多科学和工程应用程序提供显着的性能改进。在FPGA上执行硬件任务图包括两个步骤。第一步是映射步骤，如果有多个实现变体可用，则为每个任务选择适当的硬件实现。第二步是有效地将硬件任务安排到多个FPGA配置中。这项研究调查了HPRC系统的硬件任务映射和调度优化机制，以提高性能。在这项研究中，提出了一种硬件任务调度技术，即已知的减少数据移动调度（RDMS），以在实际约束下最大化性能。 RDMS将硬件任​​务调度到最少数量的配置中，并显着减少了配置间的通信。此外，RDMS利用任务之间的数据依赖性来形成更长的管道，以提高每个单个配置的吞吐量。与现有的调度方法相比，基于使用随机生成的数据流图进行的仿真，RDMS被证明可减少多达46％的配置间通信。通过在实际的带宽和FPGA参数（包括Cray XD1和SRC-6）的带宽和FPGA参数的实际约束下，通过仿真实际应用中的任务图，N体仿真，证明了该算法的实用性和效率。通过合并架构变体的硬件库引入的。同一硬件任务的多种实现变体实现了所消耗的硬件资源与任务执行吞吐量之间的折衷。开发了一种基于遗传算法（GA）的映射方法，以在合理的时间内找到接近最佳的解决方案，即任务实现的组合。每个染色体代表硬件任务及其实现变体之间的可能映射。从三个不同的可重新配置平台（SGI RC100，SRC-6和Cray XD1）中使用体系结构约束的实际数字，例如互连带宽和重新配置时间。结果表明，与为每个任务选择固定的实现变体相比，执行时间最多可提高78.6％。

著录项

  • 作者

    Huang, Miaoqing.;

  • 作者单位

    The George Washington University.;

  • 授予单位 The George Washington University.;
  • 学科 Computer Science.
  • 学位 Ph.D.
  • 年度 2009
  • 页码 122 p.
  • 总页数 122
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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