To increase the applicability of support vector machines (SVMs) in embedded systems, a scalable architecture for both SVM training and classification is proposed and tested on FPGA. The parallelism of the algorithms is extracted based on the MapReduce paradigm and mapped to multiple processing units working in parallel. Experiments show that the proposed architecture can solve SVM training and classification problems effectively with fixed-point arithmetic and good scalability can be achieved.%为了提高支持向量机(SVM)在嵌入环境中的适用性,提出了一种用于SVM训练和分类的可扩展硬件架构,并基于FPGA平台测试了其性能.基于映射-归约(MapReduce)模型分析提取出SVM算法中的并行性,并进一步映射至多个并行处理单元.实验表明,该架构可基于定点运算单元有效地完成SVM训练和分类,并具有良好的可扩展性.
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