在芯片制造工艺中，参数扰动影响了集成电路（Integrated Circuit，IC）成品率，使不同参数成品率间存在着此消彼长的相互制约关系，而目前IC参数成品率优化算法却主要局限于单一优化目标问题。本文提出一种基于工艺参数扰动的参数成品率多目标优化算法。该算法针对漏电功耗成品率及芯片时延成品率，首先构建具有随机相关性的漏电功耗及芯片时延统计模型；随后根据其相互制约特性建立基于切比雪夫仿射理论的参数成品率多目标优化模型；最后利用自适应加权求和得到分布均匀的帕雷托优化解。实验结果表明，该算法对于具有不同测试单元的实验电路均可求得大约30个分布均匀的帕雷托优化解，不仅能够有效权衡多个优化目标间的相互制约关系，还可以使传统加权求和优化方法在帕雷托曲线变化率较小之处得到优化解。%Process variations lead to a significant degradation of IC parametric yield,and they also tend to cause a nega-tive correlation between different parametric yields.However,previous yield optimization works are limited to deal with single objective problem.To deal with the above-mentioned limitation,this paper proposes a multi-objective optimization framework for co-optimization of power and timing yields under process variations.The proposed method starts with establishing explicit statistical models for power and timing metrics respectively.Then considering the negative correlation between the metrics,we employ Chebyshev affine arithmetic to formulate a multi-objective optimization model,optimize power and timing yields sim-ultaneously by adaptive weighted sum method,and provide a well-distributed set of Pareto-optimal solutions.Experimental re-sults demonstrate that the proposed method explores about 30 well-distributed solutions for each benchmark circuit with differ-ent test units.In addition,it can not only balance the restricted correlation between multiple optimization objectives,but make the traditional weighted sum method to get optimal solutions on the Pareto curve where change rate is small.
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