A verification platform's design of network processor based on systemverilog is presented in this paper.The platform is based on VMM, relational modules and the code of functional coverage are accomplished by SystemVerilog. Meanwhile, some SVA is inserted in designing code. When the network processor is running, from verification platform, the error can be discovered quickly and the verification of function can be achieved availably.%描述了一种基于SystemVerilog的网络处理器验证平台设计.该验证平台基于VMM架构,采用SystemVerilog语言编写所需的验证组件和功能覆盖率代码,并在设计代码中插入断言(SVA),将两者结合起来,能够快速、准确的定位出网络处理器在执行过程中发生的错误,有效对其进行功能验证.
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