In order to improve the working efficiency of a cryptographic embedded processor, a harvard-architectural Cache design, which includes instruction Cache (iCache) and data Cache (dCache), is proposed. Based on dual-port RAM and some low-cost hardware, label storages and data/instruction storages are designed, and control flows of iCache and dCache are given as well. 4KB iCache and 8KB dCache are configured when implemented and integrated in the cryptographic embedded processor. The FPGA validation shows that the design can satisfy the practical demand of the processor. The performance analysis shows that the access speed after adopting Cache is improved at least 5. 26 times than that of accessing main memory directly.%为了提高密码嵌入式处理器的运行效率,给出了一种哈佛结构的高速缓存(Cache)设计,包括指令Cache (iCache)和数据Cache (dCache).采用双端口RAM和较低的硬件开销设计了标签存储器和指令/数据存储器,并描述了iCache和dCache控制流程.实现时配置iCache容量为4KB、dCache容量为8KB,并完成了向密码嵌入式处理器的集成.FPGA验证结果表明其满足处理器的应用要求；性能分析结果表明,采用Cache比处理器直接访问主存在速度上至少提高5.26倍.
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