三维芯片(3D-SIC)通过硅通孔TSV技术实现电路的垂直互连,有效提高了系统集成度和整体性能.由于三维芯片测试中,用于测试的引脚数和TSV数目以及测试时功耗的限制都对测试时间有很大的影响,拟提出一种装箱问题思想的测试方案,针对每层只有一个晶片的“单塔”结构和每层有多个晶片的“多塔”结构进行测试调度优化.该优化方案在控制测试引脚数、测试TSV数目与测试功耗的同时,能有效缩短测试时间.实验结果表明,与同类方案相比,在多种限制条件和不同结构中,都有着显著的优化结果.其中“单塔”最高优化45.28％的测试时间,“多塔”最高优化了27.78％的测试时间.%3D-SIC,which improves the system integration and overall performance validly by using the TSV technology,makes vertical interconnect circuits come true.Since the number limitation of TSVs and pins for testing and test power consumption all have effects on 3D-SIC test time,we propose a testing scheme based on the concept of container-packing problems,which can optimize the test scheduling for the "single tower" structure which only has one chip in each layer and the "multiple towers" structure which has more chips in each layer.This optimization scheme can not only control the numbers of test pins and TSVs for testing and the power consumption but also reduce test time effectively.Experimental results show that the proposed scheme has obvious optimization results:the "single tower" structure can reduce up to 45.28％ of the testing time while the "multiple towers" structure can reduce up to 27.78％.
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