随着片上系统(SoC)技术的发展,芯片内各个模块交流频繁.异步系统因功耗低、速度提升潜力大和抗干扰能力强而备受青睐,但是异步电路设计复杂,数据的跨时钟域传输是亟需解决的问题.国际上目前最流行的方式是FIFO,但随着SoC复杂度的提升,一个系统上集成上百个模块,利用FIFO将会占用大量的资源,产生很大的功耗.通过分析异步传输的特点,提出一种使用指示信号来实现跨时钟域数据传输的方法,该方法与FIFO相比,在性能不减的情况下大大降低了功耗及其复杂度.利用Verilog对两个模块(CPU和FPGA)的跨时钟域数据传输进行设计仿真,通过Xilinx公司的Vivado硬件验证了其可行性.最后通过与FIFO方式的设计进行对比,说明该方法比FIFO具有更好的应用价值.%With the development of the system on chip (SoC) technology,the communication among chip modules is frequent.Asynchronous systems are popular due to low power consumption,speed up potential and strong anti-jamming capability,however,the design is complex and the problem of crossclock-domain data transmission needs to solve.At present the most popular way is the first input first output (FIFO).As the complexity of the SoC increases,there are hundreds of modules.So a system integration using the FIFO consumes disproportionate resources and power.Through the analysis of the characteristics of asynchronous transmission,we propose a way to use indicator signals to achieve crossclock-domain data transmission.Compared with the FIFO,the proposal can reduce power consumption and its design complexity without performance decrease.Simulations on the two chip modules (CPU and FPGA) using Verilogon and the Vivado hardware of Xilinx company verify its feasibility.Compared with the design of the FIFO method,the proposed method has better application value.
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