This paper focuses on the research of the fault injection methodology,the system-simulation technique and the FPGA prototypical validation approach about the TMR structure.Thanks to the fault injection logic circuitry added to the original TMR structure,the fault injection control signals of all TMR registers considered as the system’s inputs and uni-fied naming,by random generating error injection information and indexing corresponding TMR registers,the faults can be injected into any TMR group hidden to programmers in the SOC.In order to real-time check the injecting faults and to ana-lyze the faulty circuit behavior,the reference points and observation ones of all TMR registers need to become the system's outputs.To solve the problem of the limited number of pins connecting the host computer to the FPGA board,a fault injec-tion controller and a fault collection module are designed.According to a concrete fault injection case,some effective test pro-grams can be written to validate design correctness.The experimental results indicate the rate of the failure is about 18.6%, which is a basis to evaluate system dependability.%从系统验证和 FPGA 物理原型验证两个方面，分析了 TMR 结构的注错方式及其验证方法；通过在 TMR 结构中嵌入注错逻辑，并将所有组 TMR 寄存器的注错控制信号统一命名，作为系统的输入，根据随机生成的注错信息，索引对应的 TMR 寄存器，可实现向对用户透明的任意 TMR 组中注错；将每组 TMR 寄存器的参考点和观测点引到设计的顶层统一命名，作为待测系统的输出，可适时观测对应 TMR 寄存器组的注错情况，分析故障电路的行为；为了解决调试机与 FPGA 板连接的引脚数受限的问题，特别设计了注错控制器和故障收集器；根据具体的注错情况，可编写对应的测试程序，验证设计的正确性，实验结果表明，SOC 系统的错误故障率约占18．6％；为系统的可靠性评估提供了依据。
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