文章是对基于FPGA的信号质心的解算程序进行设计；以FPGA作为数据处理及控制中心对信号进行解算处理和控制各种时序;本系统采用VHDL语言编写程序,要解算信号的质心,首先要对从AD转换得到的数据进行处理,然后FPGA对这些数据进行累加及乘积累加处理；以将解算结果按优先级顺序实时写入FIFO中去,最后通过网口将已处理的数据输出到计算机中:程序经过仿真测试后表明,可用FPGA对信号进行求取质心的运算.%This article is a FPGA- hased signal centroid solver design. The FPGA as data processing and control center of the signal solver processing and control various timing. The system uses the VHDI. language programming, to solve the signal centroid, we must first get the data from the AD converter for processing, Then in the FPGA do processing these data of accumulation and product accumulation. To write the results of the solver in order of priority in real-time into the FIFO, and finally through the Ethernet port to output processed data to a computer. The program shows that FPGA can be used to compute the centroid of singal after a simulation lest.
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