Overview of Energy-Efficient Successive-Approximation Analog-to-Digital Converters:State-of-the-Art and a Design Example

Sheng-Gang Dong; Xiao-Yang Wang; Hua Fan; Jun-Feng Gao; Qiang Li

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Overview of Energy-Efficient Successive-Approximation Analog-to-Digital Converters:State-of-the-Art and a Design Example

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This paper makes a review of state-of-the-arts designs of successive-approximation register analog-to-digital converters (SAR ADCs). Methods and technique specifications are collected in view of innovative ideas. At the end of this paper, a design example is given to illustrate the procedure to design an SAR ADC. A new method, which extends the width of the internal clock, is also proposed to facilitate different sampling frequencies, which provides more time for the digital-to-analog convert (DAC) and comparator to settle. The 10 bit ADC is simulated in 0.13μm CMOS process technology. The signal-to-noise and distortion ratio (SNDR) is 54.41 dB at a 10 MHz input with a 50 MS/s sampling rate, and the power is 330μW.

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《电子科技学刊》|2013年第4期|372-381|共10页
作者
Sheng-Gang Dong; Xiao-Yang Wang; Hua Fan; Jun-Feng Gao; Qiang Li;
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作者单位

the Centre for Communication Circuits and Systems, University of Electronic Science and Technology of China, Chengdu 610054, China;

the Centre for Communication Circuits and Systems, University of Electronic Science and Technology of China, Chengdu 610054, China;

the Centre for Communication Circuits and Systems, University of Electronic Science and Technology of China, Chengdu 610054, China;

the Centre for Communication Circuits and Systems, University of Electronic Science and Technology of China, Chengdu 610054, China;

the Centre for Communication Circuits and Systems, University of Electronic Science and Technology of China, Chengdu 610054, China;

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Overview of Energy-Efficient Successive-Approximation Analog-to-Digital Converters:State-of-the-Art and a Design Example

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