A C-band frequency source based on DDS has been designed in this article, with the reference generated by the DDS chip AD9912, which drives the PLL to synthesize the output frequency of C-band. In this design, DDS is chosen to meet the requirement of small frequency step, and the PLL is then to multiply the reference frequency generated by DDS to satisfy the need of output frequency. And by the combination of DDS and PLL, the requirement of wide band, small frequency step, low phase noise and low spur emission can be achieved at the same time. Through experiments and tests, this frequency source is able to synthesize the output frequency from 6.75 MHz to 7.75 GHz by the frequency step of 1 kHz, with the phase noise at ―95 dBc/Hz@10 kHz and spur emission at -70 dBc. Compared with traditional PLL, reaching the same level of frequency and small step, this frequency source is able to realize the requirement of wide band, better spur emission and phase noise performance.%设计一款基于直接数字频率合成(DDS)驱动的C波段频率源,该频率源使用AD9912 DDS芯片产生低频参考,通过驱动锁相环产生C波段的频率输出.其中,DDS作为驱动可以保证频率综合器足够细小的分辨率,锁相环作为可变次数倍频器可完成对参考频率的频率倍增,从而在C波段范围下同时实现宽频带、小步进、低相位噪声与低杂散的指标要求.通过实验与测试,该频率源可以1kHz为频率步进实现6.75~7.75GHz的频率输出范围,其相位噪声达到―95dBc/Hz@10kHz,杂散抑制度达到70dBc.即与典型的锁相环结构相比,在同样的频率步进与输出频率下,实现了宽频带,并获得了更好的杂散表现与相位噪声.
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