• 主题
高级搜索  >
历史搜索 清空历史
首页> 外文学位 >Low phase noise design techniques for phase locked loop based integrated RF frequency synthesizers.
【24h】

Low phase noise design techniques for phase locked loop based integrated RF frequency synthesizers.

机译：用于基于锁相环的集成RF频率合成器的低相位噪声设计技术。

获取原文
获取原文并翻译 | 示例
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

The explosive growth of wireless communication market today has brought an increasing demand for high performance radio-frequency integrated circuits (RFIC) at low cost. As a result, there is a great interest in integrating the various blocks of a communication system on a single chip transceiver. One of the most difficult components to integrate is the frequency synthesizer that generates the local oscillator (LO) carrier signal. The difficulty comes mostly from the very stringent phase noise performance requirements of the wireless application.; In this dissertation, we are interested in improving phase noise performance of integrated phase-locked-loop (PLL) based radio-frequency (RF) frequency synthesizers. The most important phase noise contributors in a PLL are voltage controlled oscillator (VCO) and Phase Frequency Detector/Charge Pump/Frequency Dividers (PFD/CP/Divider). In this dissertation, we focus on the analysis of the phase noise generation mechanism in these key building blocks and the derivation of the analytical relationship between their phase noise performance and circuit design parameters. For VCO, based on the understanding of phase noise generation process in cross-coupled CMOS LC VCO, a simple yet accurate analytical phase noise model was proposed and a closed form formula for the fitting factor in Leeson's model is derived. For PFD/CP/Divider, due to the presence of many digital components, their phase noise model is studied from the point of view of timing fitter. The analytic equation that relates the PFD/CP/Divider 1 Hz normalized phase noise floor and circuit parameters is derived. Based on the theoretical analysis, the design schemes for optimizing the phase noise performance are proposed and verified by simulation and experimental prototype measurement.
机译：当今无线通信市场的爆炸性增长带来了对低成本低成本高性能射频集成电路（RFIC）的日益增长的需求。结果，在单个芯片收发器上集成通信系统的各个模块引起了极大的兴趣。集成最困难的组件之一是生成本地振荡器（LO）载波信号的频率合成器。困难主要来自无线应用对相位噪声性能的严格要求。在本文中，我们对改善基于集成锁相环（PLL）的射频（RF）频率合成器的相位噪声性能感兴趣。 PLL中最重要的相位噪声源是压控振荡器（VCO）和相位频率检测器/电荷泵/频率分频器（PFD / CP /分频器）。本文重点分析了这些关键构件的相位噪声产生机理，并推导了它们的相位噪声性能与电路设计参数之间的解析关系。对于VCO，基于对交叉耦合CMOS LC VCO中相位噪声产生过程的理解，提出了一个简单而准确的解析相位噪声模型，并推导了Leeson模型中拟合因子的封闭形式公式。对于PFD / CP /除法器，由于存在许多数字组件，因此将从时序拟合器的角度研究其相位噪声模型。推导了将PFD / CP /分频器1 Hz归一化相位本底噪声和电路参数相关的解析方程。在理论分析的基础上，提出了优化相位噪声性能的设计方案，并通过仿真和实验样机测试进行了验证。

著录项

  • 作者

    Kong, Weixin.;

  • 作者单位

    University of Maryland, College Park.;

  • 授予单位 University of Maryland, College Park.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2005
  • 页码 115 p.
  • 总页数 115
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 无线电电子学、电信技术;
  • 关键词

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号