为了探究硬件木马对集成电路芯片的危害，针对现有硬件木马设计规模相对较大、容易被检测等问题，提出了一种新的硬件木马设计。利用线性反馈移位寄存器生成的最大周期递归序列作为木马的激活序列，以在密码芯片中注入故障作为攻击手段，设计了一种规模可控的硬件木马电路。在 FPGA芯片上实现的 AES加密电路中植入木马，使用主流的基于K-L变换的硬件木马检测方法进行测试。实验结果表明，该设计具有很好的抗逻辑测试和抗旁路检测能力。%To explore the danger of Hardware Trojan to integrated circuit,and to solve the problem that existing Trojan is relatively large and easy to detect,a novel Hardware Trojan design technique is proposed.By using the maximum period of recursive sequence generated by Linear Feedback Shift Register as a Trojan activation sequence,and by implanting a failure in cryptographic chip as a means of attack,a Troj an whose scale can be controlled is designed.The Troj an is implanted in the AES encryption circuit which is implemented on FPGA chip, and tested by the mainstream Hardware Trojan detection method based on K-L transform. Experimental results show that this design has a good capability of anti-logic test and anti-side-channel detection.
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